Hi,

The project website for fpu100 at opencores.org says that the fpu is
pipelined.
Does that mean that it is possible to give the next set of operands to
the fpu before the required number of cycles are over.
For a project, I would ideally want to give new operands every cycle
though the latency might still be 8 for add/sub, 35 for sqrt etc.
Is such a thing possible/ what modifications would I have to make.

Advait