--- In 32bit_fpu@yahoogroups.com, "advaitjain" <advaitjain@...> wrote:
>
>
> Hi,
>
> The project website for fpu100 at opencores.org says that the fpu is
> pipelined.
> Does that mean that it is possible to give the next set of operands to
> the fpu before the required number of cycles are over.
> For a project, I would ideally want to give new operands every cycle
> though the latency might still be 8 for add/sub, 35 for sqrt etc.
> Is such a thing possible/ what modifications would I have to make.
>
> Advait
>

Hi Advait,

Sorry for replying late. For some operations e.g. addition/subtraction
(somebody please correct me if I am wrong), you don't have to wait
until the FPU is finished with its current operation, while some you
have to wait. The FPU is pipelined in the sense that the FPU core is
divided into independent stages with registers in between, and
therefore has the potential to execute multiple operations
simultaneously with some minor modifications. Hint: add some extra
registers. The FPU was able to work with a relative fast 100MHz
operating frequency, because it's pipelined. It wouldn't have even
reached 7 MHz if the core wasn't pipelined.


Cheers,
Jidan