When I synthesize the FPU design, I get 572 Warnings from XST. Using fpu.srcand fpu.prj (attached), I run the following: xst -ifn fpu.src -ofn fpu.log Attached...
Hi, I synthesized the FPU using Quartus II and got 367 warnings. All 367 warnings were of one type: Reduced register x with stuck data_in port to stuck value...
hi jidan, Can you please tell me How to get ADDER and MULTIPLIER module seperatly ????? I have tried my level best to do this by changing output mux. But its...
I have a doubt though. I was looking to the post_norm_addsub.vhd code. For me it is not clear when do you leave numbers denormalized. I mean, if you need a...
Hi Jeronimo, Yes, the exponent can go negative, but its adjusted in the post-normalization module. I have done it so to maximzie speed and at the same time...
Hi SHIVKARAN, Thanks for your email. There was an initializing probem and now its fixed. Download fpu_v15.zip. In the file fpu.vhd, you should find the output...
Hi Jidan, It was the postnormalization step what I was looking to, but I can't find the place where you prevent the exponent from being negative. Can you...
Hi, I can successfully synthesis the codes in Quartus II 6.0. But when I synthesize it in Quartus II 6.0 and Synlify Pro 8.5, I but the following error...
Note: forwarded message attached. ... Yahoo! Messenger with Voice. PC-to-Phone calls for ridiculously low rates. Hi, I can successfully synthesis the codes in...
Ok, in the "post_norm_addsub.vhd" the following lines do the job: -- check if shifting is needed s_shr1 <= s_fract_28_i(27); s_shl <= '1' when s_fract_28_i(27...
hi jidan, ... multiplication is not working .Please notice that i am using Xilinx ISE 7.1 tool. I have tried my level best to do this by changing output ... ...
... Hi, I actually simulated the FPU core with ModelSim and the synthesis with Quartus II. What is the problem exactly? Is it that you can't synthesis it, or...
I have already send these questions to Jidan but i post them here for everybody. So, I'm actually trying to implement fpu100 on a actel fpga (synthesizing it...
Hello, This email message is a notification to let you know that a file has been uploaded to the Files area of the 32bit_fpu group. File : /fpu_v16.zip ...
32bit_fpu@yahoogroups...
Jun 14, 2006 8:56 am
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Hello Pierre, Sorry for replying late. ... yet. ... Some signals had "X" bits, becasue they weren't used at all.There wasn't any arthimetic done with "X"...
So, After running 1)maketest.bat then 2) fpusim.bat; then i get some U then X on the output_o.You can see it on the picture i let in the folder misc. I suppose...
... The FPU core has a reset signal, only its called "start_i". And the FSM should be initialized when ever you initialize start_i. This is the process for the...
hi all, i am doing a project on fft. in that i need to convert floating point i/p to binary. i written code by using REAL data type(VHDL) . it was simulated...
Hi Ramanand ! What i can say : -The type real is not synthesisable. (it would have been to simple otherwise) but some ieee designers are working on it for the...
thanks for ur reply but u have given in c. is in there any vhdl code for same propblem. please reply me apa450 <buhasp@...> wrote: Hi Ramanand ! What i...
Hi everyone, @Pierre ... error is the LSB) ... I only modified the functions which prints the output. I never touched the functions which does the arthematic....
hi i studied ur material which is kept in this group. but i did not understood about left shift operation in add and div. Afrac=1.0000; Bfrac=0.0011; ...
HI I DIDNOT UNDERSTAND HOW TO GIVE THE EXPONENT VALUES. IF I WANT TO GIVE EXPONENTS AS exponent of a= 2**3 how to pass the values ? am i give 130 (= 3+127) or...
Hi, FPU documentation, Page 4: "A bias of 127 is added to the actual exponent to make negative exponents possible without using a sign bit. So for example if...
Quartus II 4.0 with Service Pack 1.0 - Synthesis Tool. Program writen in C to run few thousands floating point tests. Arguments and expected results where...
Hi Janusz, I am happy that it worked for you, but I didn't fully understand what you mean. The result is only valid when the ready_o signal goes high. So, are...
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