hi jidan, ... multiplication is not working .Please notice that i am using Xilinx ISE 7.1 tool. I have tried my level best to do this by changing output ... ...
... Hi, I actually simulated the FPU core with ModelSim and the synthesis with Quartus II. What is the problem exactly? Is it that you can't synthesis it, or...
I have already send these questions to Jidan but i post them here for everybody. So, I'm actually trying to implement fpu100 on a actel fpga (synthesizing it...
Hello, This email message is a notification to let you know that a file has been uploaded to the Files area of the 32bit_fpu group. File : /fpu_v16.zip ...
32bit_fpu@yahoogroups...
Jun 14, 2006 8:56 am
25
Hello Pierre, Sorry for replying late. ... yet. ... Some signals had "X" bits, becasue they weren't used at all.There wasn't any arthimetic done with "X"...
So, After running 1)maketest.bat then 2) fpusim.bat; then i get some U then X on the output_o.You can see it on the picture i let in the folder misc. I suppose...
... The FPU core has a reset signal, only its called "start_i". And the FSM should be initialized when ever you initialize start_i. This is the process for the...
hi all, i am doing a project on fft. in that i need to convert floating point i/p to binary. i written code by using REAL data type(VHDL) . it was simulated...
Hi Ramanand ! What i can say : -The type real is not synthesisable. (it would have been to simple otherwise) but some ieee designers are working on it for the...
thanks for ur reply but u have given in c. is in there any vhdl code for same propblem. please reply me apa450 <buhasp@...> wrote: Hi Ramanand ! What i...
Hi everyone, @Pierre ... error is the LSB) ... I only modified the functions which prints the output. I never touched the functions which does the arthematic....
hi i studied ur material which is kept in this group. but i did not understood about left shift operation in add and div. Afrac=1.0000; Bfrac=0.0011; ...
HI I DIDNOT UNDERSTAND HOW TO GIVE THE EXPONENT VALUES. IF I WANT TO GIVE EXPONENTS AS exponent of a= 2**3 how to pass the values ? am i give 130 (= 3+127) or...
Hi, FPU documentation, Page 4: "A bias of 127 is added to the actual exponent to make negative exponents possible without using a sign bit. So for example if...
Quartus II 4.0 with Service Pack 1.0 - Synthesis Tool. Program writen in C to run few thousands floating point tests. Arguments and expected results where...
Hi Janusz, I am happy that it worked for you, but I didn't fully understand what you mean. The result is only valid when the ready_o signal goes high. So, are...
Hello Jidan, I modified fpu.vhd stage machine, so the ready state stays until next reset. -- FSM process(clk_i) begin if rising_edge(clk_i) then if s_start_i...
hi all, when i am playing with the below progarm. i crossed all stages like simulation. but finally the synthesizer stopped me. so, my team players help me to...
Hi ! If you really want to synthesize your xyz entity, use a counter instead of a while loop which is a part of the non synthesisable subset of the vhdl...
Hello, This email message is a notification to let you know that a file has been uploaded to the Files area of the 32bit_fpu group. File : /fpu_v17.zip ...
32bit_fpu@yahoogroups...
Jul 16, 2006 7:40 am
43
Hello diode1, After the "ready_o" signal goes high, the value stored in the output register should NOT change unless you put the "start_i" signal high. Cheers,...
Hello together I am newbie in FPGA programming and after reading the theory and trying some small projects in Quartus II and the Cyclone EP1C6Q22408C I tried...
Hello Jidan Thank you for your response. I am using MS-Windows Professional. In Quartus, Version 5.0 I get the following messages: Info: Found 2 design units,...
Hello Jidan Thank you for your response. I am using MS-Windows Professional. In Quartus, Version 5.0 I get the following messages: Info: Found 2 design units,...
The mistakes you have done are: 1) You tried to synthesize simulation files! Simulation files are only for simulation in a digital simulator like modelsim,...
Hello Jidan Than you for your help. OK, I understand . I know the documentation and did it according to the suggested order but I also added the test bench:-)....
Hello Geri, ... example ... Now, you have just to input the operands and control signals. See "tb_fpu.vhd" in the directory test_bench for how this is done....
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