HI I DIDNOT UNDERSTAND HOW TO GIVE THE EXPONENT VALUES. IF I WANT TO GIVE EXPONENTS AS exponent of a= 2**3 how to pass the values ? am i give 130 (= 3+127) or...
Hi, FPU documentation, Page 4: "A bias of 127 is added to the actual exponent to make negative exponents possible without using a sign bit. So for example if...
Quartus II 4.0 with Service Pack 1.0 - Synthesis Tool. Program writen in C to run few thousands floating point tests. Arguments and expected results where...
Hi Janusz, I am happy that it worked for you, but I didn't fully understand what you mean. The result is only valid when the ready_o signal goes high. So, are...
Hello Jidan, I modified fpu.vhd stage machine, so the ready state stays until next reset. -- FSM process(clk_i) begin if rising_edge(clk_i) then if s_start_i...
hi all, when i am playing with the below progarm. i crossed all stages like simulation. but finally the synthesizer stopped me. so, my team players help me to...
Hi ! If you really want to synthesize your xyz entity, use a counter instead of a while loop which is a part of the non synthesisable subset of the vhdl...
Hello, This email message is a notification to let you know that a file has been uploaded to the Files area of the 32bit_fpu group. File : /fpu_v17.zip ...
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Jul 16, 2006 7:40 am
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Hello diode1, After the "ready_o" signal goes high, the value stored in the output register should NOT change unless you put the "start_i" signal high. Cheers,...
Hello together I am newbie in FPGA programming and after reading the theory and trying some small projects in Quartus II and the Cyclone EP1C6Q22408C I tried...
Hello Jidan Thank you for your response. I am using MS-Windows Professional. In Quartus, Version 5.0 I get the following messages: Info: Found 2 design units,...
Hello Jidan Thank you for your response. I am using MS-Windows Professional. In Quartus, Version 5.0 I get the following messages: Info: Found 2 design units,...
The mistakes you have done are: 1) You tried to synthesize simulation files! Simulation files are only for simulation in a digital simulator like modelsim,...
Hello Jidan Than you for your help. OK, I understand . I know the documentation and did it according to the suggested order but I also added the test bench:-)....
Hello Geri, ... example ... Now, you have just to input the operands and control signals. See "tb_fpu.vhd" in the directory test_bench for how this is done....
... Mmh, you stated that the testbench (tb_fpu) should not be synthesized and now you're suggesting to use it? ... That's actual the main issue! Perhaps you...
Hello Jidan Thank you very much for your infos and the hints to the solution to my problem. From the point of theory I think to understand your suggestions. ...
... Hi, Actually, the reminder is already there! Check rmndr_i in post_norm_div.vhd. I think all you have to do is postnorm it. I should have done it myself,...
Hello Jidan, Thank you for your reply. IEEE764 defines remainder as x - ny, where n is an integer closest to x/y. I am having trouble getting softfloat value...
No, I think all you have to do is shift right/left. I suggest you try a simple division that can be calculated by pencil and paper, then you check what rmndr_i...
Hi, I am sorry for replying late. Unfortunatly, I also don't know any 64-bit FPU. But I can tell you that changing a 32-bit(signle precision) FPU to a 64-bit...
hi wonder if anyone has this working on a xilinx fpga and how mutch room it would take up spesificaly a xs3s400 i need to know how mutch room would be left for...
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