Hello together I am newbie in FPGA programming and after reading the theory and trying some small projects in Quartus II and the Cyclone EP1C6Q22408C I tried...
Hello Jidan Thank you for your response. I am using MS-Windows Professional. In Quartus, Version 5.0 I get the following messages: Info: Found 2 design units,...
Hello Jidan Thank you for your response. I am using MS-Windows Professional. In Quartus, Version 5.0 I get the following messages: Info: Found 2 design units,...
The mistakes you have done are: 1) You tried to synthesize simulation files! Simulation files are only for simulation in a digital simulator like modelsim,...
Hello Jidan Than you for your help. OK, I understand . I know the documentation and did it according to the suggested order but I also added the test bench:-)....
Hello Geri, ... example ... Now, you have just to input the operands and control signals. See "tb_fpu.vhd" in the directory test_bench for how this is done....
... Mmh, you stated that the testbench (tb_fpu) should not be synthesized and now you're suggesting to use it? ... That's actual the main issue! Perhaps you...
Hello Jidan Thank you very much for your infos and the hints to the solution to my problem. From the point of theory I think to understand your suggestions. ...
... Hi, Actually, the reminder is already there! Check rmndr_i in post_norm_div.vhd. I think all you have to do is postnorm it. I should have done it myself,...
Hello Jidan, Thank you for your reply. IEEE764 defines remainder as x - ny, where n is an integer closest to x/y. I am having trouble getting softfloat value...
No, I think all you have to do is shift right/left. I suggest you try a simple division that can be calculated by pencil and paper, then you check what rmndr_i...
Hi, I am sorry for replying late. Unfortunatly, I also don't know any 64-bit FPU. But I can tell you that changing a 32-bit(signle precision) FPU to a 64-bit...
hi wonder if anyone has this working on a xilinx fpga and how mutch room it would take up spesificaly a xs3s400 i need to know how mutch room would be left for...
Hi, I haven't tried it on Xilinx yet. The XC3S400 has 8064 Equivelnt Logic Cells (LC). On Altera Cyclone, the FPU took about 4400 LC's, with the square-root...
Hi All, I am trying to synthesis the FPU using standard cells. I am wondering if someone has had the chance to do it before using design_compiler from synopsys...
... All your questions are already answered in the FPU documentation. Here the answers again: 1)Yes, it works with synplify. 2)Yes, there are testbenches. ...
--Ahmad Nour answered (through emailing me) with: Thanks Jidan for your time. But I am not talking about synplify, I am talking about Synopsys ( ASIC / Std....
Oh sorry... Snyplfiy and Synopsys sounded the same to me and I was tired when I read it ;) Anyway,the VHDL code should be synthesisable without regard to what...
The deactivation part is what I am after :) How do I deactivate everything except the multiplier for example. p.s The FPU synthesizes with around 260 Warning...
The warning messages are harmless. Regarding the deactivation, I have uploaded a FAQ file with the question you asked and of course the answer. Cheers, Jidan ...
Hi jidan, We are having trouble inputting the numbers.How do you input the floating point numbers? We are doing it in VHDL language.How do we convert the...
Hi, I think that is mentioned in the documention. Not only do you have to convert it to binary, but also to a IEEE-754 binary format. Use a special caluclator...
Hi Jidan, Thanyou for your last mail.We were having trouble converting the floating point numbers to binary.Do you have the code for it? If possible can we get...
... converting the floating point numbers to binary.Do you have the code for it? If possible can we get the code for addition and subtraction of FPU in VHDL. ...
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