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Messages 72 - 104 of 148   Oldest  |  < Older  |  Newer >  |  Newest
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72
Hi, How easy/hard is it to program a 64-bit FPU ? Also is it possible to get an open source 64-bit FPU ? Thanks...
fernanp2000
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Dec 2, 2006
8:39 pm
73
Hi, I am sorry for replying late. Unfortunatly, I also don't know any 64-bit FPU. But I can tell you that changing a 32-bit(signle precision) FPU to a 64-bit...
Jidan Al-Eryani
jidan123
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Dec 11, 2006
11:37 pm
74
hi wonder if anyone has this working on a xilinx fpga and how mutch room it would take up spesificaly a xs3s400 i need to know how mutch room would be left for...
lostaccountagainsostu...
lostaccounta...
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Dec 13, 2006
2:36 am
75
... The numbers should be very similar. Just try is out in your ISE. ... not very much. Perhaps the FPU will not fit into the xs3s400. Martin...
Martin Schoeberl
jopdesign
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Dec 13, 2006
8:01 am
76
Hi, I haven't tried it on Xilinx yet. The XC3S400 has 8064 Equivelnt Logic Cells (LC). On Altera Cyclone, the FPU took about 4400 LC's, with the square-root...
Jidan Al-Eryani
jidan123
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Dec 14, 2006
12:07 am
77
Hi All, I am trying to synthesis the FPU using standard cells. I am wondering if someone has had the chance to do it before using design_compiler from synopsys...
nour_ahmed
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Dec 21, 2006
10:37 pm
78
... All your questions are already answered in the FPU documentation. Here the answers again: 1)Yes, it works with synplify. 2)Yes, there are testbenches. ...
Jidan Al-Eryani
jidan123
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Dec 27, 2006
3:26 pm
79
--Ahmad Nour answered (through emailing me) with: Thanks Jidan for your time. But I am not talking about synplify, I am talking about Synopsys ( ASIC / Std....
Jidan Al-Eryani
jidan123
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Dec 27, 2006
11:47 pm
80
Oh sorry... Snyplfiy and Synopsys sounded the same to me and I was tired when I read it ;) Anyway,the VHDL code should be synthesisable without regard to what...
Jidan Al-Eryani
jidan123
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Dec 28, 2006
12:14 am
81
The deactivation part is what I am after :) How do I deactivate everything except the multiplier for example. p.s The FPU synthesizes with around 260 Warning...
Ahmed Nour
nour_ahmed
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Dec 28, 2006
12:48 am
82
The warning messages are harmless. Regarding the deactivation, I have uploaded a FAQ file with the question you asked and of course the answer. Cheers, Jidan ...
Jidan Al-Eryani
jidan123
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Dec 29, 2006
2:52 am
83
Hi jidan, We are having trouble inputting the numbers.How do you input the floating point numbers? We are doing it in VHDL language.How do we convert the...
SHILPA SHIVARAM
shilvrinda
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Jan 7, 2007
5:12 pm
84
Hi, I think that is mentioned in the documention. Not only do you have to convert it to binary, but also to a IEEE-754 binary format. Use a special caluclator...
Jidan Al-Eryani
jidan123
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Jan 15, 2007
6:23 am
85
Hi Jidan, Thanyou for your last mail.We were having trouble converting the floating point numbers to binary.Do you have the code for it? If possible can we get...
SHILPA SHIVARAM
shilvrinda
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Jan 18, 2007
2:00 pm
86
... converting the floating point numbers to binary.Do you have the code for it? If possible can we get the code for addition and subtraction of FPU in VHDL. ...
Jidan Al-Eryani
jidan123
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Jan 21, 2007
7:38 am
87
hi jidan . i am very much confused with the exception unit in floating point unit. we have to do seperate module for exception unit or we can combine the...
sathraj_29
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Feb 1, 2007
9:46 am
88
... I am sorry, but I didn't write any verilog code for the FPU. Cheers, Jidan...
Jidan Al-Eryani
jidan123
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Feb 3, 2007
12:48 pm
89
Hi, The project website for fpu100 at opencores.org says that the fpu is pipelined. Does that mean that it is possible to give the next set of operands to the...
advaitjain
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Mar 5, 2007
11:06 am
90
Hello sir . Thank u for ur mail. We can give the next set of operands only after the number of cycles completed. The modifications to be done in the project...
satheesh kumar
sathraj_29
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Mar 6, 2007
9:06 am
91
... Hi Advait, Sorry for replying late. For some operations e.g. addition/subtraction (somebody please correct me if I am wrong), you don't have to wait until...
Jidan Al-Eryani
jidan123
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Mar 14, 2007
10:27 pm
92
Hello, This email message is a notification to let you know that a file has been uploaded to the Files area of the 32bit_fpu group. File : /fpu_v19.zip ...
32bit_fpu@yahoogroups...
Send Email
Apr 26, 2007
12:35 pm
93
Jidan, is this corretion also in the CVS? Martin...
Martin Schoeberl
jopdesign
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Apr 26, 2007
9:31 pm
94
No, I still didn't. When I uploaded the code, I tried also to update the CVS, but the program I use (WinCVS), always crashed. I will try to solve this over the...
Jidan Al-Eryani
jidan123
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Apr 27, 2007
6:53 pm
95
... serial multiplier is used (thanks to Chris Basson!) ... Done! Thank you...
Jidan Al-Eryani
jidan123
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Apr 27, 2007
9:22 pm
96
... serial multiplier is used (thanks to Chris Basson!) ... Done! Thanks, please keep this list informed when you update your FPU as I'm also including it in...
Martin Schoeberl
jopdesign
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Apr 29, 2007
9:27 am
99
The instructions for getting test vectors suggest running timesoftfloat. However, that program was designed not to test the accuracy of the results, just to...
thirtyninewinks
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Jun 14, 2007
5:59 pm
101
I've gotten the fpu-100 core to work using Modeltech (on Linux), but I haven't been able to get the included test-bench to work. This because of my limited...
dara.parsavand
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Jun 20, 2007
2:01 am
102
It is working now. I'm not sure what the difference between my build environment at work and at home is, but I have it working at home (Ubuntu 7.04/i386) now....
dara.parsavand
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Jun 20, 2007
7:09 am
103
I do not have the problem of no vectors testing the square root (a 100 in the third line of the text block), but I have the same repetition issue you mentioned...
dara.parsavand
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Jun 20, 2007
11:03 pm
104
... I skimmed the file timesoftfloat.c fpu_v19 and from John Hauser. The line: minIterations = 1000 is changed to minIterations = 100000 and there are some...
dara.parsavand
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Jun 21, 2007
5:00 pm
Messages 72 - 104 of 148   Oldest  |  < Older  |  Newer >  |  Newest
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