Hi jidan,

           We are having trouble inputting the numbers.How do you input the floating point numbers? We are doing it in VHDL language.How do we convert the decimal numbers to binary numbers? .

Send free SMS to your Friends on Mobile from your Yahoo! Messenger. Download Now! http://messenger.yahoo.com/download.php

The warning messages are harmless. Regarding the deactivation, I have
uploaded a FAQ file with the question you asked and of course the answer.

Cheers,
Jidan

--- In 32bit_fpu@yahoogroups.com, "Ahmed Nour" <ahmed.nour@...> wrote:
>
> The deactivation part is what I am after :)
> How do I deactivate everything except the multiplier for example.
>
> p.s The FPU synthesizes with around 260 Warning in Synopsys. Also, a big
> chunk of the warnings are about "registers that are constants".
>
>
>
> On 12/27/06, Jidan Al-Eryani <jidan@...> wrote:
> >
> >   Oh sorry... Snyplfiy and Synopsys sounded the same to me and I
was tired
> > when I read it ;) Anyway,the VHDL code should be synthesisable without
> > regard to what software you use, thats why you have standards.
Best thing is
> > just to try it.
> >
> > Regarding your second question: *How do you test each arthimetic unit
> > seperatly?*
> >
> >
> > *Answer:*
> > If you go to folder "test_bench" you will find readme.txt, there
it says:
> >
> > *To test the FPU core, do the following:
> >
> > 1)    Build timesoftfloat.exe for your specific platform(read
instructions
> > in folder SoftFloat for howto do that).
> >     Before you do that, try the already included file.
> >
> > 2)    Create the testcases by running maketest.bat in folder
test_bench.
> > Default value is 100000 cases for each
> >     arithmetic operation and for each rounding mode. This comes up
to 2
> > million test cases.
> >
> > 3)     run fpusim.bat to simulate and test the FPU core using
modelsim.*
> >
> > Step 2) creates the testcases by executing maketest.bat. So, all
you have
> > to do is edit this file. For example, if you want to test just the
> > multiplication unit, this file should contain only those files:
> >
> > *timesoftfloat -nearesteven float32_mul > testcases.txt
> > timesoftfloat -tozero float32_mul >> testcases.txt
> > timesoftfloat -up float32_mul >> testcases.txt
> > timesoftfloat -down float32_mul >> testcases.txt*
> >
> > Four lines for each rounding mode.
> >
> > BTW, if you actually want to operate the FPU with, for example,
just the
> > multiplier, you can deactivate all other units with no problem as all
> > arthimetic units are indepenant from each other. This way you can save
> > silicon area.
> >
> > Cheers,
> > Jidan
> >
> > --- In 32bit_fpu@yahoogroups.com, "Jidan Al-Eryani" <jidan@> wrote:
> > >
> > > --Ahmad Nour answered (through emailing me) with:
> > >
> > > Thanks Jidan for your time.
> > > But I am not talking about synplify, I am talking about Synopsys (
> > > ASIC / Std. cell ) design compiler.
> > > As for the testbenchs, I am not clear I can find the testbenchs. Is
> > > there a testbench that can check the functionality of the Multiplier
> > > as a standalone entity, not inside the FPU ? If yes, then please
> > > direct me to where I can find it.
> > > Thanks
> > >
> > > --- In 32bit_fpu@yahoogroups.com, "Jidan Al-Eryani" jidan@ wrote:
> > > >
> > > > --- In 32bit_fpu@yahoogroups.com, "nour_ahmed" <ahmed.nour@>
wrote:
> > > > >
> > > > > Hi All,
> > > > > I am trying to synthesis the FPU using standard cells. I am
> > wondering
> > > > > if someone has had the chance to do it before using
design_compiler
> > > > > from synopsys ?
> > > > >
> > > > > I am also wondering if I need to test subcomponents, like the
> > > > > multiplier , adder or divider, are there any testbenches
available
> > to
> > > > > these components ?
> > > > >
> > > > > Thanks.
> > > > > Ahmed Youssef
> > > > >
> > > >
> > > > All your questions are already answered in the FPU
documentation. Here
> > > > the answers again:
> > > > 1)Yes, it works with synplify.
> > > > 2)Yes, there are testbenches.
> > > >
> > > > Jidan
> > > >
> > >
> >
> >
>

--Ahmad Nour answered (through emailing me) with:

Thanks Jidan for your time.
But I am not talking about synplify, I am talking about Synopsys (
ASIC / Std. cell ) design compiler.
As for the testbenchs, I am not clear I can find the testbenchs. Is
there a testbench that can check the functionality of the Multiplier
as a standalone entity, not inside the FPU ? If yes, then please
direct me to where I can find it.
Thanks

--- In 32bit_fpu@yahoogroups.com, "Jidan Al-Eryani" <jidan@...> wrote:
>
> --- In 32bit_fpu@yahoogroups.com, "nour_ahmed" <ahmed.nour@> wrote:
> >
> > Hi All,
> > I am trying to synthesis the FPU using standard cells. I am wondering
> > if someone has had the chance to do it before using design_compiler
> > from synopsys ?
> >
> > I am also wondering if I need to test subcomponents, like the
> > multiplier , adder or divider, are there any testbenches available to
> > these components ?
> >
> > Thanks.
> > Ahmed Youssef
> >
>
> All your questions are already answered in the FPU documentation. Here
> the answers again:
> 1)Yes, it works with synplify.
> 2)Yes, there are testbenches.
>
> Jidan
>

--- In 32bit_fpu@yahoogroups.com, "nour_ahmed" <ahmed.nour@...> wrote:
>
> Hi All,
> I am trying to synthesis the FPU using standard cells. I am wondering
> if someone has had the chance to do it before using design_compiler
> from synopsys ?
>
> I am also wondering if I need to test subcomponents, like the
> multiplier , adder or divider, are there any testbenches available to
> these components ?
>
> Thanks.
> Ahmed Youssef
>

All your questions are already answered in the FPU documentation. Here
the answers again:
1)Yes, it works with synplify.
2)Yes, there are testbenches.

Jidan

Hi All,
I am trying to synthesis the FPU using standard cells. I am wondering
if someone has had the chance to do it before using design_compiler
from synopsys ?

I am also wondering if I need to test subcomponents, like the
multiplier , adder or divider, are there any testbenches available to
these components ?

Thanks.
Ahmed Youssef

Hi,

I haven't tried it on Xilinx yet. The XC3S400 has 8064 Equivelnt Logic
Cells (LC). On Altera Cyclone, the FPU took about 4400 LC's, with the
square-root deactivted, about 3500 LC's. So, if it was the same as
Cyclone, you should have sufficient space for a simple CPU (with
MicroBlaze definatly). As martin said, its best to check it out
yourself with Xilinix ISE.
Cheers,
Jidan

<achiestdragon@...> wrote:
>
> hi wonder if anyone has this working on a xilinx fpga
> and how mutch room it would take up
>
> spesificaly a xs3s400
> i need to know how mutch room would be left for other things
> like a cpu and i/o
>
> David
>

> hi wonder if anyone has this working on a xilinx fpga
> and how mutch room it would take up

The numbers should be very similar. Just try is out
in your ISE.

>
> spesificaly a xs3s400
> i need to know how mutch room would be left for other things
> like a cpu and i/o

not very much. Perhaps the FPU will not fit into the xs3s400.

Martin

hi wonder if anyone has this working on a xilinx fpga
and how mutch room it would take up

spesificaly a xs3s400
i need to know how mutch room would be left for other things
like a cpu and i/o

David

Hi,

I am sorry for replying late. Unfortunatly, I also don't know any
64-bit FPU. But I can tell you that changing a 32-bit(signle
precision) FPU to a 64-bit (double precision), is not that hard.

Cheers,
Jidan

--- In 32bit_fpu@yahoogroups.com, "fernanp2000" <fernanp2000@...> wrote:
>
> Hi,
>
> How easy/hard is it to program a 64-bit FPU ?
> Also is it possible to get an open source 64-bit FPU ?
>
>
> Thanks
>

Hi,

How easy/hard is it to program a 64-bit FPU ?
Also is it possible to get an open source 64-bit FPU ?


Thanks

No, I think all you have to do is shift right/left.
I suggest you try a simple division that can be calculated by pencil
and paper, then you check what rmndr_i looks like. Looking in the
divider unit (serial_div.vhd) might make a couple of things clear.
Unfortunatly, if you would have asked me 1 month earlier about the
reminder, I might have written the code for you, since I did have the
time.

--- In 32bit_fpu@yahoogroups.com, "stevenj_jin" <stevenj_jin@...> wrote:
>
> Hello Jidan,
>
> Thank you for your reply.
>
> IEEE764 defines remainder as x - ny, where n is an integer
> closest to x/y.
>
> I am having trouble getting softfloat value of rem from
> rmndr_i. Do you think perhaps I need to divide again
> with a new integer value I get from the first division cycle
> and get the remainder?
>
> Thank you,
> Steven
>
> --- In 32bit_fpu@yahoogroups.com, "Jidan Al-Eryani" <jidan@>
> wrote:
> >
> > --- In 32bit_fpu@yahoogroups.com, "stevenj_jin" <stevenj_jin@>
> wrote:
> > >
> > > Can anyone shed a light on how to implement a floating point
> > > remainder(FMOD) from this 32bit FPU module?
> > >
> > > Thank you
> > >
> > Hi,
> > Actually, the reminder is already there! Check rmndr_i in
> > post_norm_div.vhd. I think all you have to do is postnorm it. I
> should
> >  have done it myself, but I just didn't find the time, and it
> wasn't
> > part of my project assignemnt,but I will add it sometime in the
> future.
> >
> > Cheers,
> > Jidan
> >
>

Hello Jidan,

Thank you for your reply.

IEEE764 defines remainder as x - ny, where n is an integer
closest to x/y.

I am having trouble getting softfloat value of rem from
rmndr_i. Do you think perhaps I need to divide again
with a new integer value I get from the first division cycle
and get the remainder?

Thank you,
Steven

--- In 32bit_fpu@yahoogroups.com, "Jidan Al-Eryani" <jidan@...>
wrote:
>
> --- In 32bit_fpu@yahoogroups.com, "stevenj_jin" <stevenj_jin@>
wrote:
> >
> > Can anyone shed a light on how to implement a floating point
> > remainder(FMOD) from this 32bit FPU module?
> >
> > Thank you
> >
> Hi,
> Actually, the reminder is already there! Check rmndr_i in
> post_norm_div.vhd. I think all you have to do is postnorm it. I
should
>  have done it myself, but I just didn't find the time, and it
wasn't
> part of my project assignemnt,but I will add it sometime in the
future.
>
> Cheers,
> Jidan
>

--- In 32bit_fpu@yahoogroups.com, "stevenj_jin" <stevenj_jin@...> wrote:
>
> Can anyone shed a light on how to implement a floating point
> remainder(FMOD) from this 32bit FPU module?
>
> Thank you
>
Hi,
Actually, the reminder is already there! Check rmndr_i in
post_norm_div.vhd. I think all you have to do is postnorm it. I should
  have done it myself, but I just didn't find the time, and it wasn't
part of my project assignemnt,but I will add it sometime in the future.

Cheers,
Jidan

Can anyone shed a light on how to implement a floating point
remainder(FMOD) from this 32bit FPU module?

Thank you

--- In 32bit_fpu@yahoogroups.com, "pal4vlsi" <pal4vlsi@...> wrote:
>
> hii..
>
>  I was given a project of designing high speed 32-bit floating point
> adders using VERILOG..
>  I am confused on whether to check for the
> exceptions(infinity,NaN,....) before comparing exponents or after
> addition of two no.s.

You check for exception before AND after.

>  I have to submit the code by next week and am running short of time.
> i will be indebted to you if you provide source code for Floating
> point adders (in Verilog)
>

Sorry, but mine is in VHDL.

hii..

  I was given a project of designing high speed 32-bit floating point
adders using VERILOG..
  I am confused on whether to check for the
exceptions(infinity,NaN,....) before comparing exponents or after
addition of two no.s.
  I have to submit the code by next week and am running short of time.
i will be indebted to you if you provide source code for Floating
point adders (in Verilog)

>> But now, these are libraries but how should a program look like for
> example
>> to solve the equation y = Sqrt(a * b);?
>
> Now, you have just to input the operands and control signals. See
> "tb_fpu.vhd" in the directory test_bench for how this is done. The

Mmh, you stated that the testbench (tb_fpu) should not
be synthesized and now you're suggesting to use it?

> For example, the square root is done as following:
>
> start_i <= '1';
> opa_i <= "01000001001000000000000000000000";  --10
> fpu_op_i <= "100"; --set arthemtic operation. Here square root.
> rmode_i <= "00"; --set rounding mode. Here round to nearest even
******
> wait for CLK_PERIOD; -- wait for one clock cycle then...
******
> start_i <= '0'; --Note that the FPU starts calculating the operands at
> the input after the start signal goes 0.
******
> wait until ready_o='1'; --when the ready signal goes 1, you know that
******
> the answer at the ouput register is ready

> Note: Replace the "wait" command with hardware friendly commands, e.g.

That's actual the main issue!
Perhaps you can provide the state machine example instead
of a testbench to show how to use the FPU for an actual
problem that the OP wants to solve.

Martin

Hello Geri,

> But now, these are libraries but how should a program look like for
example
> to solve the equation y = Sqrt(a * b);?

Now, you have just to input the operands and control signals. See
"tb_fpu.vhd" in the directory test_bench for how this is done. The
above operation is actually two operations.
1) mulitply a by b
2) sqrt the answer

For example, the square root is done as following:

start_i <= '1';
opa_i <= "01000001001000000000000000000000";  --10
fpu_op_i <= "100"; --set arthemtic operation. Here square root.
rmode_i <= "00"; --set rounding mode. Here round to nearest even
wait for CLK_PERIOD; -- wait for one clock cycle then...
start_i <= '0'; --Note that the FPU starts calculating the operands at
the input after the start signal goes 0.
wait until ready_o='1'; --when the ready signal goes 1, you know that
the answer at the ouput register is ready

Note: Replace the "wait" command with hardware friendly commands, e.g.
a state machine. Tell me if you have understood it now. The easy
questions are always the most important questions :-)

Cheers,
Jidan


--- In 32bit_fpu@yahoogroups.com, "Gerhard Burger" <geburger@...> wrote:
>
> Hello Jidan
>
>
>
> Than you for your help. OK, I understand . I know the documentation
and did
> it according to the suggested order but I also added the test bench:-).
>
>
>
> But now, these are libraries but how should a program look like for
example
> to solve the equation y = Sqrt(a * b);?
>
>
>
> Thank you again and sorry for the maybe easy questions.
>
>
>
> Geri
>
>
>
>   _____
>
> From: 32bit_fpu@yahoogroups.com [mailto:32bit_fpu@yahoogroups.com]
On Behalf
> Of Jidan Al-Eryani
> Sent: Donnerstag, 19. Oktober 2006 13:42
> To: 32bit_fpu@yahoogroups.com
> Subject: [32bit_fpu] Re: How to use the floating point library
>
>
>
> The mistakes you have done are:
>
> 1) You tried to synthesize simulation files! Simulation files are only
> for simulation in a digital simulator like modelsim, they are not for
> hardware. Don't synthesize anything in the folder "test_bench".
>
> 2) There is a specified order in which you should compile your files.
> See p.18 in the included doc.
>
> Cheers,
> Jidan
>
> --- In 32bit_fpu@yahoogrou <mailto:32bit_fpu%40yahoogroups.com>
ps.com, Geri
> Frick <gcoolfire@> wrote:
> >
> > Hello Jidan
> >
> > Thank you for your response. I am using MS-Windows Professional.
> >
> > In Quartus, Version 5.0 I get the following messages:
> >
> > Info: Found 2 design units, including 1 entities, in source file
> sqrt.vhd
> > Info: Found design unit 1: sqrt-rtl
> > Info: Found entity 1: sqrt
> > Info: Found 2 design units, including 1 entities, in source file
> post_norm_sqrt.vhd
> > Info: Found design unit 1: post_norm_sqrt-rtl
> > Info: Found entity 1: post_norm_sqrt
> > Info: Found 1 design units, including 0 entities, in source file
> comppack.vhd
> > Info: Found design unit 1: comppack
> > Info: Found 2 design units, including 1 entities, in source file
fpu.vhd
> > Info: Found design unit 1: fpu-rtl
> > Info: Found entity 1: fpu
> > Info: Elaborating entity "tb_fpu" for the top level hierarchy
> > Warning: Verilog HDL or VHDL warning at tb_fpu.vhd(159):
> combinational loop found on net clk_i.
> > Error: VHDL Wait Statement error at tb_fpu.vhd(167): Wait Statement
> must contain condition clause with UNTIL keyword
> > Error: Can't elaborate top-level user hierarchy
> > Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 1
> warning
> > Error: Processing ended: Wed Oct 18 23:53:43 2006
> > Error: Elapsed time: 00:00:06
> > Error: Quartus II Full Compilation was unsuccessful. 2 errors, 1
warning
> >
> >
> > Attached a screen shot of Quartus
> >
> >
> > Thank you very much for your feedback an help
> >
> > Geri
> >
> >
> >
> >
> >
> >
> > __________________________________________________________
> > Der frühe Vogel fängt den Wurm. Hier gelangen Sie zum neuen Yahoo!
> Mail: http://mail. <http://mail.yahoo.de> yahoo.de
> >
>

The mistakes you have done are:

1) You tried to synthesize simulation files! Simulation files are only
for simulation in a digital simulator like modelsim, they are not for
hardware. Don't synthesize anything in the folder "test_bench".

2) There is a specified order in which you should compile your files.
See p.18 in the included doc.


Cheers,
Jidan

--- In 32bit_fpu@yahoogroups.com, Geri Frick <gcoolfire@...> wrote:
>
> Hello Jidan
>
> Thank you for your response. I am using MS-Windows Professional.
>
> In Quartus, Version 5.0 I get the following messages:
>
> Info: Found 2 design units, including 1 entities, in source file
sqrt.vhd
>             Info: Found design unit 1: sqrt-rtl
>             Info: Found entity 1: sqrt
> Info: Found 2 design units, including 1 entities, in source file
post_norm_sqrt.vhd
>             Info: Found design unit 1: post_norm_sqrt-rtl
>             Info: Found entity 1: post_norm_sqrt
> Info: Found 1 design units, including 0 entities, in source file
comppack.vhd
>             Info: Found design unit 1: comppack
> Info: Found 2 design units, including 1 entities, in source file fpu.vhd
>             Info: Found design unit 1: fpu-rtl
>             Info: Found entity 1: fpu
> Info: Elaborating entity "tb_fpu" for the top level hierarchy
> Warning: Verilog HDL or VHDL warning at tb_fpu.vhd(159):
combinational loop found on net clk_i.
> Error: VHDL Wait Statement error at tb_fpu.vhd(167): Wait Statement
must contain condition clause with UNTIL keyword
> Error: Can't elaborate top-level user hierarchy
> Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 1
warning
>             Error: Processing ended: Wed Oct 18 23:53:43 2006
>             Error: Elapsed time: 00:00:06
> Error: Quartus II Full Compilation was unsuccessful. 2 errors, 1 warning
>
>
> Attached a screen shot of Quartus
>
>
> Thank you very much for your feedback an help
>
> Geri
>
>
>
>
>
>
> ___________________________________________________________
> Der frühe Vogel fängt den Wurm. Hier gelangen Sie zum neuen Yahoo!
Mail: http://mail.yahoo.de
>

Hello Jidan

Thank you for your response. I am using MS-Windows Professional.

In Quartus, Version 5.0 I get the following messages:

Info: Found 2 design units, including 1 entities, in source file sqrt.vhd
             Info: Found design unit 1: sqrt-rtl
             Info: Found entity 1: sqrt
Info: Found 2 design units, including 1 entities, in source file
post_norm_sqrt.vhd
             Info: Found design unit 1: post_norm_sqrt-rtl
             Info: Found entity 1: post_norm_sqrt
Info: Found 1 design units, including 0 entities, in source file comppack.vhd
             Info: Found design unit 1: comppack
Info: Found 2 design units, including 1 entities, in source file fpu.vhd
             Info: Found design unit 1: fpu-rtl
             Info: Found entity 1: fpu
Info: Elaborating entity "tb_fpu" for the top level hierarchy
Warning: Verilog HDL or VHDL warning at tb_fpu.vhd(159): combinational loop
found on net clk_i.
Error: VHDL Wait Statement error at tb_fpu.vhd(167): Wait Statement must contain
condition clause with UNTIL keyword
Error: Can't elaborate top-level user hierarchy
Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 1 warning
             Error: Processing ended: Wed Oct 18 23:53:43 2006
             Error: Elapsed time: 00:00:06
Error: Quartus II Full Compilation was unsuccessful. 2 errors, 1 warning


Attached a screen shot of Quartus


Thank you very much for your feedback an help

Geri






___________________________________________________________
Der frühe Vogel fängt den Wurm. Hier gelangen Sie zum neuen Yahoo! Mail:
http://mail.yahoo.de

Hi Geri,

Can you please tell me what OS you are using and what the error
message was?

Cheers,
Jidan

--- In 32bit_fpu@yahoogroups.com, "Geri" <gcoolfire@...> wrote:
>
> Hello together
>
> I am newbie in FPGA programming and after reading the theory and
> trying some small projects in Quartus II and the Cyclone
> EP1C6Q22408C I tried to do mathematics with floating point. In my
> case I try to calculate the equation
>
> y:=sqrt(a*b);
>
> So I found this very interesting floating point library in the
> internet but although reading the documentation I am not able to get
> it running in Quartus with my knowledge. I would be very happy if
> someone olf you would be so kind and send me me a link or a zipped
> file to/with a very small project. The included batch file also does
> not work in my case.
>
> Thank your very much for your help and I would really be happy if I
> get your library working
>
> Geri
>

Hello together

I am newbie in FPGA programming and after reading the theory and
trying some small projects in Quartus II and the Cyclone
EP1C6Q22408C I tried to do mathematics with floating point. In my
case I try to calculate the equation

y:=sqrt(a*b);

So I found this very interesting floating point library in the
internet but although reading the documentation I am not able to get
it running in Quartus with my knowledge. I would be very happy if
someone olf you would be so kind and send me me a link or a zipped
file to/with a very small project. The included batch file also does
not work in my case.

Thank your very much for your help and I would really be happy if I
get your library working

Geri

Hello diode1,

After the "ready_o" signal goes high, the value stored in the output
register should NOT change unless you put the "start_i" signal high.

Cheers,
Jidan

--- In 32bit_fpu@yahoogroups.com, "diode1" <always_friend@...> wrote:
>
> Hello Jidan,
>       I modified fpu.vhd stage machine, so the ready state stays until
> next reset.
>
>  -- FSM
>  process(clk_i)
>  begin
> 	 if rising_edge(clk_i) then
> 		 if s_start_i ='1' then
> 			 s_state <= busy;
> 			 s_count <= 0;
> 		 -- change - added JR
> 			 ready_o <= '0';
> 		 elsif s_count=5 and ((fpu_op_i="000") or (fpu_op_i="001")) then
> 			 s_state <= waiting;
> 			 ready_o <= '1';
> 			 s_count <=0;
> 		 elsif s_count=MUL_COUNT and fpu_op_i="010" then
> 			 s_state <= waiting;
> 			 ready_o <= '1';
> 			 s_count <=0;
> 		 elsif s_count=33 and fpu_op_i="011" then
> 			 s_state <= waiting;
> 			 ready_o <= '1';
> 			 s_count <=0;
> 		 elsif s_count=33 and fpu_op_i="100" then
> 			 s_state <= waiting;
> 			 ready_o <= '1';
> 			 s_count <=0;
> 		 elsif s_state=busy then
> 			 s_count <= s_count + 1;
> 		 else
> 			 s_state <= waiting;
> 	 -- change !!!! JR
> 			 ready_o <= '1';
> 		 end if;
>  end if;
>  end process;
>
> Regards,
> Janusz.
>
>
> --- In 32bit_fpu@yahoogroups.com, "Jidan Al-Eryani" <jidan@> wrote:
> >
> > Hi Janusz,
> >
> > I am happy that it worked for you, but I didn't fully understand what
> > you mean. The result is only valid when the ready_o signal goes high.
> > So, are you saying that the ready_o signal went high too early? What
> > did you change in the code to solve the problem?
> >
> > Cheers,
> > Jidan
> >
> >
> > --- In 32bit_fpu@yahoogroups.com, "diode1" <always_friend@> wrote:
> > >
> > > --- In 32bit_fpu@yahoogroups.com, "diode1" <always_friend@> wrote:
> > > >
> > > > Quartus II 4.0 with Service Pack 1.0 - Synthesis Tool.
> > > >
> > > > Program writen in C to run few thousands floating point tests.
> > > > Arguments and expected results where generated on PC machine and
> > > > results are stored in test table.
> > > > Multiplication and division failes with fpu hardware
implementation.
> > > > It passes with software library.
> > > >
> > > > Any comments?
> > > >
> > > > Thanks Janusz.
> > > >
> > >
> > > Problem solved!
> > > Read result port to early.
> > >
> > > J.
> > >
> >
>

Hello,

This email message is a notification to let you know that
a file has been uploaded to the Files area of the 32bit_fpu
group.

   File        : /fpu_v17.zip
   Uploaded by : jidan123 <jidan@...>
   Description : 1)Corrected bug related to adding two denormalized operands.

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http://groups.yahoo.com/group/32bit_fpu/files/fpu_v17.zip

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Regards,

jidan123 <jidan@...>

Hi !

If you really want to synthesize your xyz entity, use a counter
instead of a while loop which is a part of the non synthesisable
subset of the vhdl langage !
And What it is use for ? No output... So it seems that it's a
testbench... !

Ciiao

Pierre

--- In 32bit_fpu@yahoogroups.com, ramanand reddy <rams_nandu@...> wrote:
>
> hi all,
>
> when i am playing with the below progarm.
> i crossed all stages like simulation.
> but finally the synthesizer stopped me.
> so, my team players help me to reach the goal.
>
>
> i faced a problem with WHILE LOOP while doing the synthesis
(simulation ok).
>
> see the synthesis report below....
>
> Analyzing Entity <add> (Architecture <ar_add>).
> ERROR:Xst:1312 - Loop has iterated 64 times. Use "set
-loop_iteration_limit XX" to iterate more
>
> ERROR: XST failed
> Process "Synthesize" did not complete.
>
> -------------see the program  below  -----------------
>
>
>
> library ieee ;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_unsigned.all;
> use ieee.std_logic_misc.all;
> use ieee.std_logic_arith.all;
> use ieee.numeric_std.all;
>
>
> entity xyz is
>     Port ( clk:in std_logic);
> end xyz;
>
> architecture Behavioral of xyz is
> begin
>
> process(clk)
>
> variable frac :std_logic_vector(9 downto 0):="0001100001";
> variable diff  :std_logic_vector(5 downto 0):="010010";
> variable expo  :std_logic_vector(5 downto 0):="010000";
>
> begin
>
>  while(expo > "00000")loop  -------------or use-----------  expo  /=
"00000"
>
>     expo := expo + "00001";
>      frac := '0' & frac(9 downto 1);
>      expo  := expo - "00001";
>
>    end loop;
>     end process;
> end Behavioral;
>
>
>
> ok players try to play the game.
>
> byyyyyyyyyyyyy
>
>
>
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