Dear Colleagues,

Programming the Phytec C167CS development board we have
problems with program variables.
We can read only that variables which were
stored in CPU registers.  In the case when the compiler
put the variables in an external memory we always get back
the 0xFFFF value.

We wondering to now what configuration is needed
to solve the problem.

         Many thanks,
             Dénes Fodor
                 Hungary

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we have enhanced our on-line bit timing calculation tool
for CANary  (ATMEL CAN controller) at:

http://www.port.de/deutsch/canprod/sv_req_form.html

Stephen Mac Neil wrote:
>
> I am learning to communicate CAN using a T89C51CC01 micro. I am having
> difficulty understanding the bit timing to implement a particular
> transmission rate. I have tried to work the example on the manufacturers
> data sheet (page 83) and my numbers don't add up. Any help on this would be
> greatly appreciated.
>
> Stephen Mac Neil
> DynGen Technologies Inc
>
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with best regards / mit freundlichen Grüßen

    Heinz-Jürgen Oertel

===========================================
Heinz-Jürgen Oertel
port GmbH            phone +49 345 77755-0
Regensburger Str. 7c fax   +49 345 77755-20
D-06132 Halle/Saale  mailto:oe@...
Germany              http://www.port.de
===========================================
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 Hello,
        I'd like to use the Vector 'CANcardX CANalyzer' in my  desktop PC. I guess I need a "PCMCIA adapter for ISA or PCI bus". Could someone point me to any vendors who sell such an adapter card?

Or is it simpler to buy a regular PCI or ISA CAN controller card?
 
 
 
 
 Regards,
 
 Hareesh Jana,
 DCS Applications Group,
 Texas Instruments,
 Houston, TX - USA.

We've used the Greystone Carddock product along with the Vector cards with
good success:
http://www.grystone.com/site/products/pcmcia.html
<http://www.grystone.com/site/products/pcmcia.html>

-----Original Message-----
From: Spunaugle Brian [mailto:bspunaugle@...]
Sent: Tuesday, June 26, 2001 1:01 PM
To: 'canlist@...'
Subject: RE: [CANLIST] PCMCIA adapter for ISA or PCI bus


Hareesh,

My company just purchased such an adapter from Vector.
Contact them for more info.

Brian Spunaugle
Electrical Engineer

Acu-Rite Inc USA

  -----Original Message-----
From: Janakiraman, Hareesh [mailto:hareesh@...]
Sent: Tuesday, June 26, 2001 10:08 AM
To: 'canlist@...'
Subject: [CANLIST] PCMCIA adapter for ISA or PCI bus



  Hello,
         I'd like to use the Vector 'CANcardX CANalyzer' in my  desktop PC. I
guess I need a "PCMCIA adapter for ISA or PCI bus". Could someone point me
to any vendors who sell such an adapter card?

Or is it simpler to buy a regular PCI or ISA CAN controller card?




  Regards,

  Hareesh Jana,
  DCS Applications Group,
  Texas Instruments,
  Houston, TX - USA.




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 Hello,
        I'd like to use the Vector 'CANcardX CANalyzer' in my  desktop PC. I guess I need a "PCMCIA adapter for ISA or PCI bus". Could someone point me to any vendors who sell such an adapter card?

Or is it simpler to buy a regular PCI or ISA CAN controller card?
 
 
 
 
 Regards,
 
 Hareesh Jana,
 DCS Applications Group,
 Texas Instruments,
 Houston, TX - USA.

Thank you for the reply. I am sorry that I had skip
this archive while I am researching.
I was looking for an automatic calculation for CRC. I
am doing a test of modifying DLC
and calculating its CRC value. I had prepared a
checklist and I like to test our program
if it can check an error message: (DLC is 3 but the
Data field has 2bytes.)
Do you have this automatic CRC calculation tool?


Jericho B. Fenix wrote:
> I am looking for CRC calculation tool for checking
CRC
> codes.

It's in the archive (september 98)... but I'll send it
again.

Knut
---------------------- Forwarded by Knut
Roll-Lund/Horten/Norcontrol/NO on
25/06/2001 12:31 ---------------------------
Subject:  Re: [CAN] CRC for CAN

Hi Patrick ALLARD-JACQUIN,

Here is a program I made when I first tried to
understand a can message as
seen on a logic analyzer, I posted this also to
comp.arch embedded earlier
this year. It is not a practical implementation but it
works (the example
message is one, as I saw it on the logic-analyzer,
with stuff bits and all)
The CRC is calculated for each bit in the destuff()
funtion (stuff bits are
skipped at end of this function).

Knut Roll-Lund

PS. Sorry for the length of this but I thought that it
was not too long, so...

/* Knut Roll-Lund 1994 */
#include <dir.h>
#include <stdio.h>
#include <stdlib.h>
#include <conio.h>
#include <string.h>

char message[]=
{  0,                               //sof
    0,0,0,0,1,0,0,0,0,0,1,0,1,       //id
    0,                               //rtr
    0,0,                             //reserved
    1,0,0,0,                         //data length
    0,0,1,0,0,0,0,0,1,0,             //data 0
    0,0,0,0,1,0,0,0,1,               //data 1
    0,0,0,0,0,1,0,1,0,               //data 2
    0,0,0,0,1,0,0,1,1,               //data 3
    0,0,0,0,0,1,1,0,0,               //data 4
    0,0,0,1,0,0,1,0,1,               //data 5
    0,0,0,0,0,1,1,1,0,               //data 6
    0,0,0,0,1,0,1,1,1,               //data 7
    0,1,1,1,0,0,0,0,1,0,0,0,1,0,1,   //crc
    1,                               //crc delimiter
    0,                               //ack slot
    1,                               //ack delimiter
    1,1,1,1,1,1,1                    //eof
};

char *msgptr;
static char bitcnt = 0;
static char oldbit = 1;

static unsigned short crc=0;

void destuff(void)
{
    crc<<=1;
    if (((crc&0x8000)!=0)^*msgptr)
       crc ^= 0x4599;
    crc &= 0x7fff;

    if (oldbit==*msgptr)
       bitcnt++;
    else
    {
       oldbit=*msgptr;
       bitcnt=1;
    }
    msgptr++;
    if (bitcnt==5)
    {
       bitcnt=1;
       oldbit=*msgptr;
       msgptr++;
    }
}

void main()
{
    short tmp;
    char i,cnt,data;

    msgptr = message;
    //skip until sof (start of frame)
    while (*msgptr)
       msgptr++;
    printf("sof:        0\n");
    destuff();
    tmp=0;
    printf("id:         ");
    for (i=0; i<11; i++)
    {
       putchar('0'+*msgptr);
       tmp<<=1;
       if (*msgptr)
          tmp++;
       destuff();
    }
    printf("     = 0x%03x\n",tmp);
    printf("rtr:        %d\n",*msgptr);
    destuff();
    printf("reserved:   %d",*msgptr);
    destuff();
    printf("%d\n",*msgptr);
    destuff();
    cnt=0;
    printf("data len:   ");
    for (i=0; i<4; i++)
    {
       putchar('0'+*msgptr);
       cnt<<=1;
       if (*msgptr)
          cnt++;
       destuff();
    }
    printf("            = %d\n",cnt);
    for (;cnt;cnt--)
    {
       data=0;
       printf("data:       ");
       for (i=0; i<8; i++)
       {
          putchar('0'+*msgptr);
          data<<=1;
          if (*msgptr)
             data++;
          destuff();
       }
       printf("        = %d\n",data);
    }
    printf("calculated crc              =
0x%04x\n",crc);
    tmp=0;
    printf("crc:        ");
    for (i=0; i<15; i++)
    {
       putchar('0'+*msgptr);
       tmp<<=1;
       if (*msgptr)
          tmp++;
       destuff();
    }
    printf(" = 0x%04x\n",tmp);
    printf("crc delimi: %d\n",*msgptr);
    destuff();
    printf("ack slot:   %d\n",*msgptr);
    destuff();
    printf("ack delimi: %d\n",*msgptr);
    destuff();
}



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Hi!
I'm Zsolt from Hungary.
We make a project with this National Insturment Card.
We have two problems:
1., We can not install this card under WIN 2000. We have downloaded the new
driver(1.5) from the ni.com. With WIN 9x/NT goes.
Have anyone ideas ,what is the solution, what can we do ?
2., The card is after 1,5 hours very hot in the PCMCIA socket ,and  make
lot of errors. We have cold tha card with a fun,but not this is the right
solution.

Sorry for my english!Deutsch geht besser!

Best regards

Zsolt

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Jericho B. Fenix wrote:
> I am looking for CRC calculation tool for checking CRC
> codes.

It's in the archive (september 98)... but I'll send it again.

Knut
---------------------- Forwarded by Knut Roll-Lund/Horten/Norcontrol/NO on
25/06/2001 12:31 ---------------------------
Subject:  Re: [CAN] CRC for CAN

Hi Patrick ALLARD-JACQUIN,

Here is a program I made when I first tried to understand a can message as
seen on a logic analyzer, I posted this also to comp.arch embedded earlier
this year. It is not a practical implementation but it works (the example
message is one, as I saw it on the logic-analyzer, with stuff bits and all)
The CRC is calculated for each bit in the destuff() funtion (stuff bits are
skipped at end of this function).

Knut Roll-Lund

PS. Sorry for the length of this but I thought that it was not too long, so...

/* Knut Roll-Lund 1994 */
#include <dir.h>
#include <stdio.h>
#include <stdlib.h>
#include <conio.h>
#include <string.h>

char message[]=
{  0,                               //sof
    0,0,0,0,1,0,0,0,0,0,1,0,1,       //id
    0,                               //rtr
    0,0,                             //reserved
    1,0,0,0,                         //data length
    0,0,1,0,0,0,0,0,1,0,             //data 0
    0,0,0,0,1,0,0,0,1,               //data 1
    0,0,0,0,0,1,0,1,0,               //data 2
    0,0,0,0,1,0,0,1,1,               //data 3
    0,0,0,0,0,1,1,0,0,               //data 4
    0,0,0,1,0,0,1,0,1,               //data 5
    0,0,0,0,0,1,1,1,0,               //data 6
    0,0,0,0,1,0,1,1,1,               //data 7
    0,1,1,1,0,0,0,0,1,0,0,0,1,0,1,   //crc
    1,                               //crc delimiter
    0,                               //ack slot
    1,                               //ack delimiter
    1,1,1,1,1,1,1                    //eof
};

char *msgptr;
static char bitcnt = 0;
static char oldbit = 1;

static unsigned short crc=0;

void destuff(void)
{
    crc<<=1;
    if (((crc&0x8000)!=0)^*msgptr)
       crc ^= 0x4599;
    crc &= 0x7fff;

    if (oldbit==*msgptr)
       bitcnt++;
    else
    {
       oldbit=*msgptr;
       bitcnt=1;
    }
    msgptr++;
    if (bitcnt==5)
    {
       bitcnt=1;
       oldbit=*msgptr;
       msgptr++;
    }
}

void main()
{
    short tmp;
    char i,cnt,data;

    msgptr = message;
    //skip until sof (start of frame)
    while (*msgptr)
       msgptr++;
    printf("sof:        0\n");
    destuff();
    tmp=0;
    printf("id:         ");
    for (i=0; i<11; i++)
    {
       putchar('0'+*msgptr);
       tmp<<=1;
       if (*msgptr)
          tmp++;
       destuff();
    }
    printf("     = 0x%03x\n",tmp);
    printf("rtr:        %d\n",*msgptr);
    destuff();
    printf("reserved:   %d",*msgptr);
    destuff();
    printf("%d\n",*msgptr);
    destuff();
    cnt=0;
    printf("data len:   ");
    for (i=0; i<4; i++)
    {
       putchar('0'+*msgptr);
       cnt<<=1;
       if (*msgptr)
          cnt++;
       destuff();
    }
    printf("            = %d\n",cnt);
    for (;cnt;cnt--)
    {
       data=0;
       printf("data:       ");
       for (i=0; i<8; i++)
       {
          putchar('0'+*msgptr);
          data<<=1;
          if (*msgptr)
             data++;
          destuff();
       }
       printf("        = %d\n",data);
    }
    printf("calculated crc              = 0x%04x\n",crc);
    tmp=0;
    printf("crc:        ");
    for (i=0; i<15; i++)
    {
       putchar('0'+*msgptr);
       tmp<<=1;
       if (*msgptr)
          tmp++;
       destuff();
    }
    printf(" = 0x%04x\n",tmp);
    printf("crc delimi: %d\n",*msgptr);
    destuff();
    printf("ack slot:   %d\n",*msgptr);
    destuff();
    printf("ack delimi: %d\n",*msgptr);
    destuff();
}



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> >Hi All,
> >I am looking for a chip that can talk to a microcontroller by SPI
> > interface and has 8 I/O ports. I am appreciate any suggestion.
> >Thanks in advance.

........... SNIP ..........

> We have used a Motorola chip: MC33298. It is not cheap ($6-$8 US) but is
> very rugged. As I recall, 75V and 1A peak with lots of internal
> protections. Can be used as high current open collector outputs or add a
> pull-up resistor and any bit not turned on can be read as an input.

........... SNIP .........

> You can also use a simple CPLD such as Xilinx 9536 and make it a SPI
> to/from whatever you need. We are working on other designs which use this
> approach.

........... SNIP ..........

The CPLD solution will probably be WAY more inexpensive than the Motorola
device (and will offer wider IO). Not sure about whether the current
sourcing-sinking abilities of these CPLDs would be enough for your needs,
though. The simple PLDs such as 16V8 or 22V10 have a pretty good drive, but
their price is getting worse and worse ... I'd go for the Xilinx and buy
current drivers or TransZorbs if necessary with the rest of the money.

Nacho de los Ríos Tormo

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Hi All,

I am looking for CRC calculation tool for checking CRC
codes.
I really appreciate any suggestion.

Thanks in advance.

Jericho B. Fenix
Fujitsu Ten Software Philippines, Inc.
Software Development Engineer


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Hi All,

I am looking for CRC calculation tool for checking CRC
codes.
I really appreciate any suggestion.

Thanks in advance.

Jericho B. Fenix
Fujitsu Ten Software Philippines, Inc.
Software Development Engineer


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Hi,

Motorola has a paper on the subject.  It's document # AN1798.  It should be a help.

Good Luck,
Steve Corrigan
Texas Instruments, Inc.

-----Original Message-----
From: Stephen Mac Neil [mailto:macneil@...]
Sent: Friday, June 22, 2001 9:43 AM
To: canlist@...
Subject: [CANLIST] T89C51CC01 CAN bit timing

I am learning to communicate CAN using a T89C51CC01 micro. I am having
difficulty understanding the bit timing to implement a particular
transmission rate. I have tried to work the example on the manufacturers
data sheet (page 83) and my numbers don't add up. Any help on this would be
greatly appreciated.

Stephen Mac Neil
DynGen Technologies Inc

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Hi,

Is there anyone with some knowledge and/or experience with this Kit?

T.I.A.

--
Carlos Palminha
Engenharia de Desenvolvimento
INOV - Inesc Inovação
http://www.inov.pt


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I am learning to communicate CAN using a T89C51CC01 micro. I am having
difficulty understanding the bit timing to implement a particular
transmission rate. I have tried to work the example on the manufacturers
data sheet (page 83) and my numbers don't add up. Any help on this would be
greatly appreciated.


Stephen Mac Neil
DynGen Technologies Inc

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You should be able to buy this document from SAE www.sae.org on line.
It is included in the SAE handbook. Some libraries subscribe this SAE
handbook also.



Mohsin Jamali
Professor
Dept. of Electrical Engineering and Computer Science
The University of Toledo
Toledo, Ohio 43606


At 04:48 PM 06/21/2001 +0200, you wrote:
>Who could send me any information, or doc. about standard SAE J1939/81
>dealing with address management and allocation ?
>Thanks for your help.
>
>----------------------------------------------------------------------------
>-
>Oliviero Francesco
>Ansaldobreda - Ansaldo Trasporti s.p.a.
>Development of new Products and new Technologies
>Voice: +39 081 243 2068
>Fax: +39 081 243 2031
>Email: mailto:oliviero.francesco@...
>----------------------------------------------------------------------------
>-
>
>--
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>at http://www.vector-informatik.com/canlist/
>Problems to canlist-owner@...



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Hello Denes,

Are you sure that you did not execute EINIT before touching
SYSCON? Some ROM monitor debuggers (like Tasking's
Crossview) do execute EINIT before you can do anything. We
had to recompile the monitor sources to disable EINIT in
the monitor software. (Additionally, Tasking's startup
routine executes EINIT, too. Why...???)

A way to set up the registers:
set XPERCON value
set SYSCON value
EINIT

Best regards
M. Kares


Denes Fodor <fodor@...> írta:

> Dear colleagues,
>
> We have problem with Infineon C167CS (dual on chip CAN
controllers).
> The XPERCON register value is 0401H by default. The XPEN
bit is "1" in
> the
> SYSCON register and this not allow to use the second on
chip CAN
> controller .
> We have tried to modify the value of XPEN to "0" before
EINIT but
> without success.
>
> Can anybody help in how to change the value of
> the XPERCON register from 0401H to 0C03H.
>
>  Many thanks,
>
>     D.Fodor
>     Hungary
>
> --
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> at http://www.vector-informatik.com/canlist/
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>





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Hello,

Denes Fodor wrote:

> We have tried to modify the value of XPEN to "0" before EINIT but
> without success.

Sure? If you have a Monitor like Keil Monitor at the Phytec board
for debugging your program, this Monitor do initialize and make EINIT.
(XPEN is 0 after Reset)

--
Mit freundlichen Grüßen
Regards

Steffen Rose

=================================================================
port GmbH                     phone +49 345 777 55-0
Regensburger Str. 7c          fax   +49 345 777 55-20
D-06132 Halle (Saale)         email service@...
Germany                       www   http://www.port.de
=================================================================
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At 08:53 6/21/2001 -0400, you wrote:
>Hi All,
>I am looking for a chip that can talk to a microcontroller by SPI
interface
>and has 8 I/O ports. I am appreciate any suggestion.
>Thanks in advance.
>
>Lam Nguyen

Try the Infineon 81C90/91, it's got a parallel and SPI interface.
There's 16 bits of digital I/O too.  It doesn't support extended
identifiers.

Cheers,
Stuart

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At 08:53 6/21/2001 -0400, you wrote:
>Hi All,
>I am looking for a chip that can talk to a microcontroller by SPI interface
>and has 8 I/O ports. I am appreciate any suggestion.
>Thanks in advance.
>
>Lam Nguyen

We've rolled some simple hardware which does this from our JStamp and
controls Lego Mindstorms motors and reads the Lego sensors. Schematics are
online at http://jcx.systronix.com

You can also use a simple CPLD such as Xilinx 9536 and make it a SPI
to/from whatever you need. We are working on other designs which use this
approach.

Bruce
------- WWW.SYSTRONIX.COM ----------
   Real embedded Java and much more
      High speed 8051 systems
+1-801-534-1017  Salt Lake City, USA
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If anyone is interested in checking out a development version of a tool
for calculating the BTR values (and bus lengths) for the ST Micro ST10F168
CAN chip - and checking the values on hardware?

If so, for the next week or so, the tool can be downloaded from the web
page at:

         http://www.omegas.co.uk/CAN/st10beta.htm

There are no conditions attached to this other than that, if you take a
copy, please mail me with comments and feedback - which will be welcome.

Thanks and regards,

Mike Schofield

Tel. +44 (0)1489 893221
http://www.omegas.co.uk/CAN/

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Dear colleagues,

We have problem with Infineon C167CS (dual on chip CAN controllers).
The XPERCON register value is 0401H by default. The XPEN bit is "1" in
the
SYSCON register and this not allow to use the second on chip CAN
controller .
We have tried to modify the value of XPEN to "0" before EINIT but
without success.

Can anybody help in how to change the value of
the XPERCON register from 0401H to 0C03H.

  Many thanks,

     D.Fodor
     Hungary

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Who could send me any information, or doc. about standard SAE J1939/81
dealing with address management and allocation ?
Thanks for your help.

----------------------------------------------------------------------------
-
Oliviero Francesco
Ansaldobreda - Ansaldo Trasporti s.p.a.
Development of new Products and new Technologies
Voice: +39 081 243 2068
Fax: +39 081 243 2031
Email: mailto:oliviero.francesco@...
----------------------------------------------------------------------------
-

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Kees Zagers wrote:
> I heard from a specialist, that this is something that can happen on a
> CAN network. However I'm curious to know if someone has an explanation
> for this? And maybe also a way to prevent it from happening?
Others have explained this, it is a very unlikely situation if you are
using crystal oscillators and have the same bus timing settings.

Additional messages and not additional nodes indicates to me that this is
not the case too.

I have never seen it. We use CAL and CANopen and any domain transfer or SDO
would suffer from this happening.

If this should be the case the duplicate will follow the original before
any lower priority is allowed in.

John Dammeyer wrote:
> messages and not extra nodes.  I'd look carefully at what the messages
> are and if there is a possiblity that somehow you are sending the same
> message ID from two different nodes at the same time.  This will cause
> each node to think it owns the bus until the CRC fails at which point
> both transmitters resend.
This would typically generate a lot of error frames, bit errors (before the
CRC) unless the message is exactly the same, in which case they will come
through as one.

I would rather suspect the software and not the can controllers!

Instead of listening to the bus you could listen to the transmit pin of the
node which is supposed to send the message and see if it really sends the
duplicate.

It would also be valuable to know if there are many error frames (error
counters)

Knut Roll-Lund

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The "last but one bit bla bla bla..." definition in the Bosch CAN spec was
necessary back in those days, due to the fact that sloppy oscillators, such
as LC or RC, were allowed (they are still allowed now, of course, but not
many implementation are using them). In which case, some CAN controllers
(refer to receivers) might see the EOF earlier than others, which happens to
fall within the EOF field of the others, and start to insert the SOF onto
the bus, presumably it has something to transmit. If this definition is not
in place, then you would see a strange error frame followed after a good
frame for no reason.

Following this, the only situation that could trigger the double receiving
by the receivers is that, the message seems to be corrupted (last bit is
wrong) from the transmitter point of view. If you are *absolutely* sure that
it is not due to the software bug, then the only likely explanation is that
some other nodes have inaccurate timer and inject their SOF earlier than
they should, that annoys the transmitter. I suggest you take a look at the
transmit error counter to see if it changes.

Tang
CAN, DeviceNet, EtherNet/IP
http://www.warwick.ac.uk/devicenet


-----Original Message-----
From: canlist-owner@...
[mailto:canlist-owner@...]On Behalf Of Jerónimo Quesada
Sent: 20 June 2001 21:32
To: canlist@...
Subject: RE: [CANLIST] message twice


Hi Kees

I have some explanation:

Although the CAN bus definition is a good piece of engineering, this, I
think, is an inconsistency in the CAN bus definition, the double receiving
problem. A message is considered valid to the CAN transmitter when there is
no error until the last bit of the EOF. But the receiver considers valid a
message when there is no error until the last but one bit of the EOF. So,
when the error is in the last bit, the transmitter will retransmit and the
receiver will receive twice the same message. Really Bosh has included this
in the CAN Specification:
"MESSAGE VALIDATION
the point of time at which a message is taken to be valid, is different for
the transmitter
and the receivers of the message.
Transmitter:
The message is valid for the transmitter, if there is no error until the end
of END OF
FRAME. If a message is corrupted, retransmission will follow automatically
and
according to prioritisation. In order to be able to compete for bus access
with other
messages, retransmission has to start as soon as the bus is idle.
Receivers:

The message is valid for the receivers, if there is no error until the last
but one bit of
END OF FRAME."

I don't know any workaround at the low level, except physical layer error
analysis, probably the node is loosing synchronisation

At the application layer level the advise is:

- Don't use toggle messages

- Don't transmit messages carrying relative data (increments...)

- Take measures at the application level to handle communication of
sequences taken in account the probability of double transmit messages.

Please let me know some additional information about the bus conditions
(speed, lenght, ...),  I'm very interested in this issue. Thanks in advance

Jerónimo Quesada
j.quesada@...



----- Original Message -----
From: Kees Zagers <kees@...>
To: <canlist@...>
Sent: Wednesday, June 20, 2001 2:08 PM
Subject: [CANLIST] message twice


> Hi,
>
> In existing installation with CAN we introduced the following problem
after
> the addition of some extra messages on the bus:
>
> Every now and then a message which is transmitted by a node appears to be
on
> the network twice, allthough the software just sent it once. The existing
> software in the other nodes is reacting to this second message in an
> uncontrolled way now.
>
> I heard from a specialist, that this is something that can happen on a CAN
> network. However I'm curious to know if someone has an explanation for
this?
> And maybe also a way to prevent it from happening?
>
> By the way this installation still uses the Intel 526 controller. Would
the
> 527 (or SJA1000) controller solve the problem?
>
> Best regards
>
> /'''  |   ''/   Kees Zagers
> \__   |   /__   SI-KWADRAAT B.V.
>    \  |         kees@...
> ___/  |
> tel: +31(0)40-2631185  fax:+31(0)40-2838092
>
>
> --
> Archives, unsubscribing etc. see canlist homepage
> at http://www.vector-informatik.com/canlist/
> Problems to canlist-owner@...
>

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Hi Kees

I have some explanation:

Although the CAN bus definition is a good piece of engineering, this, I
think, is an inconsistency in the CAN bus definition, the double receiving
problem. A message is considered valid to the CAN transmitter when there is
no error until the last bit of the EOF. But the receiver considers valid a
message when there is no error until the last but one bit of the EOF. So,
when the error is in the last bit, the transmitter will retransmit and the
receiver will receive twice the same message. Really Bosh has included this
in the CAN Specification:
"MESSAGE VALIDATION
the point of time at which a message is taken to be valid, is different for
the transmitter
and the receivers of the message.
Transmitter:
The message is valid for the transmitter, if there is no error until the end
of END OF
FRAME. If a message is corrupted, retransmission will follow automatically
and
according to prioritisation. In order to be able to compete for bus access
with other
messages, retransmission has to start as soon as the bus is idle.
Receivers:

The message is valid for the receivers, if there is no error until the last
but one bit of
END OF FRAME."

I don't know any workaround at the low level, except physical layer error
analysis, probably the node is loosing synchronisation

At the application layer level the advise is:

- Don't use toggle messages

- Don't transmit messages carrying relative data (increments...)

- Take measures at the application level to handle communication of
sequences taken in account the probability of double transmit messages.

Please let me know some additional information about the bus conditions
(speed, lenght, ...),  I'm very interested in this issue. Thanks in advance

Jerónimo Quesada
j.quesada@...



----- Original Message -----
From: Kees Zagers <kees@...>
To: <canlist@...>
Sent: Wednesday, June 20, 2001 2:08 PM
Subject: [CANLIST] message twice


> Hi,
>
> In existing installation with CAN we introduced the following problem
after
> the addition of some extra messages on the bus:
>
> Every now and then a message which is transmitted by a node appears to be
on
> the network twice, allthough the software just sent it once. The existing
> software in the other nodes is reacting to this second message in an
> uncontrolled way now.
>
> I heard from a specialist, that this is something that can happen on a CAN
> network. However I'm curious to know if someone has an explanation for
this?
> And maybe also a way to prevent it from happening?
>
> By the way this installation still uses the Intel 526 controller. Would
the
> 527 (or SJA1000) controller solve the problem?
>
> Best regards
>
> /'''  |   ''/   Kees Zagers
> \__   |   /__   SI-KWADRAAT B.V.
>    \  |         kees@...
> ___/  |
> tel: +31(0)40-2631185  fax:+31(0)40-2838092
>
>
> --
> Archives, unsubscribing etc. see canlist homepage
> at http://www.vector-informatik.com/canlist/
> Problems to canlist-owner@...
>

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A message can appear on the CAN bus twice because the receiver considers
the message complete one bit time before the transmitter considers the
message complete.  In this case if the receiver figures the message is
good then it doesn't assert an error frame.  Meanwhile the transmitter
thinks the message is bad and does a resend.

Usually bus level hardware or termination causes these kinds of
problems.  But in your case you state that you've only added extra
messages and not extra nodes.  I'd look carefully at what the messages
are and if there is a possiblity that somehow you are sending the same
message ID from two different nodes at the same time.  This will cause
each node to think it owns the bus until the CRC fails at which point
both transmitters resend.

Timing and crystal tolerence could have one of the two start the second
arbitration sequence late enough that the first then succeeds followed
by the second which also succeeds and looks like there were two
identical messages transmitted.

The CAN spec has this timing anomoly between TX and RX so most likely
all nodes will have the same problem.  I'd suggest you make sure your
bus is electrically clean.

Cheers,

John Dammeyer

-----Original Message-----
From: canlist-owner@...
[mailto:canlist-owner@...] On Behalf Of Kees Zagers
Sent: Wednesday, June 20, 2001 5:08 AM
To: canlist@...
Subject: [CANLIST] message twice


Hi,

In existing installation with CAN we introduced the following problem
after the addition of some extra messages on the bus:

Every now and then a message which is transmitted by a node appears to
be on the network twice, allthough the software just sent it once. The
existing software in the other nodes is reacting to this second message
in an uncontrolled way now.

I heard from a specialist, that this is something that can happen on a
CAN network. However I'm curious to know if someone has an explanation
for this? And maybe also a way to prevent it from happening?

By the way this installation still uses the Intel 526 controller. Would
the 527 (or SJA1000) controller solve the problem?

Best regards

/'''  |   ''/   Kees Zagers
\__   |   /__   SI-KWADRAAT B.V.
    \  |         kees@...
___/  |
tel: +31(0)40-2631185  fax:+31(0)40-2838092


--
Archives, unsubscribing etc. see canlist homepage
at http://www.vector-informatik.com/canlist/
Problems to canlist-owner@...


--
Archives, unsubscribing etc. see canlist homepage
at http://www.vector-informatik.com/canlist/
Problems to canlist-owner@...

Hi,

In existing installation with CAN we introduced the following problem after
the addition of some extra messages on the bus:

Every now and then a message which is transmitted by a node appears to be on
the network twice, allthough the software just sent it once. The existing
software in the other nodes is reacting to this second message in an
uncontrolled way now.

I heard from a specialist, that this is something that can happen on a CAN
network. However I'm curious to know if someone has an explanation for this?
And maybe also a way to prevent it from happening?

By the way this installation still uses the Intel 526 controller. Would the
527 (or SJA1000) controller solve the problem?

Best regards

/'''  |   ''/   Kees Zagers
\__   |   /__   SI-KWADRAAT B.V.
    \  |         kees@...
___/  |
tel: +31(0)40-2631185  fax:+31(0)40-2838092


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