Hi Thanks for your response Unfortunately I did not get this working. I get no response, no matter if I have net_class_attr in vdrc.ini or not. But in the...
Roman PRAGER
Roman.PRAGER@...
Jun 3, 2004 5:53 am
2963
Hi I want to use the same fub several times in a drawing. The Fub I/O names is given automatically while saving a drawing, according to the connected net name....
Benny, Don't use Fubs if you need the port name in a schematic (ie. pin name in the schematic's symbol) to be different from the name of the net to which it is...
Daniel, Thank you for your answer. I am using ViewDraw only a year, and I've never used Oats (I did not succeed to activate it) What I want to do is creating a...
We have just purchased PADS and are well into the learning curve. However, we have some legacy circuits in Protel format we need to pull into PADS. Is there a...
Benny, You can use a FUB to create the filter module. Once it is done, and you have removed the SYMTYPE=FUB attribute, then copy and paste the symbol as you...
Hello there, I am trying to convert a schematic done in Concept (Cadence tool) to DxDesigner. Please let me know if any one out there has done this kind of...
www.e-tools.com E-studio product can do it ... __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam...
We did Orcad to DxDesigner using E-Studio Pro from eTools. Wasn't awesome - A ton of useless attributes came over, and we had to do significant re-work to the...
The fact is that estudio works with EDIF to translate schematics from one platform to anther platform. The big issue here is that EDIF is a language with many...
Hi Ron - We offer translation services and/or a translator to take Protel designs into PowerPCB. Alternatively, later this year, Mentor will be releasing a...
... for all the circuit inputs. I will be glad to get your recommendations. Benny, I've been using Viewlogic for around 5 years now, on some really large ...
Greetings all, I'm being asked to differentiate between the different instances of the sub-hierarchy in a design. Is there a way to propagate the value of a ...
Iestyn, Thanks, but I think you're right -- That is overkill. It adds too much info to the schematic, and the names can't be relocated so that they're not...
E-studio can work with EDIFs (200/300/400) fine . However it is doing direct translations too. In a direct translation you don't need EDIF of any sort. You...
... As a matter a fact, I'm not creating a bridge between DxDesigner and Concept but between DxDesigner and Virtuoso Schematic Composer (ASIC flow). So this...
Hi Chuck I have heard from Mentor Graphics they are working on a translator. Unfortunately we can't wait, so we either re-draw the schematics or use a ...
A much better approach is available in Viewdraw. All you need to do is use reuse blocks. The procedure is exactly similar to creating hierarchical designs....
Thank you for the explanation. Cadence's ConceptHDL is oriented towards PCB while Cadence's Virtuoso Composer is oriented towards IC. So I'm not sure if the...
As an alternative to REUSE_BLOCKS, which requires OATs... If you follow the somewhat convoluted procedure I outlined in post#2973, you end up with multiple...
Thanks all, but I got an easy solution from support (kudos to them for a fast response): I'm placing an @labeled_path attr in the title block I use for the ...
Since I installed the epd2004, I can not create a part list. After running the partlister I am getting a message as if "*.lst" file was created, but the file...
I found out that after doing something with ViewDraw I an not create part-list until resetting the computer. The problem is that I did not find yet that...
Hi, Does anyone know how to specify the following in the ViewDraw schematics so that it is passed through to either PADS or Allegro as a DRC rule: I have a...
Pin Pair rules were not designed to be supported in the interface, so I don't know of a method to do this to date, other than make it 2 nets. Gary ... From:...
Hi Gary, I believe that with Allegro, the "RELATIVE_ PROPAGATION_DELAY" attribute may very well work for what I am trying to do, but I don't know how to use...
Austin, You may be able to get something out of it with schedule. I'm currently evaluating the Allegro 'Constraint Manager', which comes as part of their PCB...
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