This is a forum for users of ESA IP Cores, maintained and moderated by the Microelectronics Section of the European Space Agency/ESTEC.This forum was created with the main purpose of free-willingly sharing experience, expertise and peer-to-peer support in the ESA IP Core users' community.

This forum should be used to post comments, suggestions, questions and answers regarding the use (code analysis, simulation, synthesis, porting to any ASIC or FPGA technology, etc) or status (interesting features or deficiencies of the code and the related documents) of any of the various ESA IP Cores (CAN, SpaceWire, OBDH, PTME, etc). Most welcome are articles describing experiences from the actual use of any of the ESA IP Cores, descriptions of problems faced and the implemented solutions, and any other feedback that can be of interest to other users.

The current offer of ESA IP Cores, the conditions and procedures to obtain a licence and then the ESA IP Core are explained in detail in the following ESA web site: http://www.esa.int/TEC/Microelectronics/SEMVWLV74TE_0.html

This forum CAN NOT be used to exchange any ESA IP Cores files or parts of files (neither source code nor any other licence-protected documents) that ESA has distributed under licence to each user.