Thanks Dear John Hi Moin Here is little more. To add more to what john has mentioned in ISE 11 that is a FIFO generator inside the core generator will help you
I should add, the number of Block RAMs depends on the size of the FPGA you are using. ... -- http://www.johnkent.com.au http://members.optusnet.com.au/jekent
Hi Moin, Sorry for the delay in replying, but I was hoping someone else might take the initiative to answer your question. I have not used the Virtex 5 FPGAs.
Hi All, I am relatively new to working on FPGAs and using VHDL. I needed to know what I should look at to help me understand how to use the Block RAMs in the