Hi Dirk,

To simulate the closer to correct clock frequencies I use different
clock dividers. These break the scandoubler developed by Tobias when
he initially ported my core to the c-one. (A long time ago in a galaxy
far far away)

So I have made a new one that is somewhat of a compromise to get both
a steady picture and allow fractional clock dividers for the CPU
(34.375 for PAL and 33 for NTSC). Simple scandoubling results in a
picture that looks like it is blended in a milkshaker. So I 'rescan'
the picture to a slightly different one, which might upset one or two
monitors 'out there'.

That said, it is not impossible to improve upon it, we just can't keep
using the simple scandoubler and support turbo loading at the same time.

As for your 'shift to the left bug', could you please test version
0.26a that is available at http://syntiac.com/fpga64.html
and tell me if it improves the picture quality for you?

Peter


--- In cone_cores@yahoogroups.com, Dirk Verwiebe <sp_rinter@...> wrote:
>
> Hallo Peter,
>
> thanks a lot for the new core.
> Unfortunately this version seems to break compatibilty to some
> vga monitors. :'(
> On my Eizo F56 the picture looks rare dark and black & white(50&60Hz).
> On the Sony 19" CRT the picture is dark but more recognizeble than on
> the Eizo.
> On both crts the picture is out of center, much more than before.
> Is there a way to get the 0.25 video compatibility back ?
>
> Grüße
>
> Dirk
>
>
>
>
>
>
> Peter schrieb:
> >
> > Hallo Allemaal,
> >
> > It has been a while since there was an update. During a long 'retro'
> > weekend Jens, BeRo and I had the chance to torture the C-One with
> > various demos, cartridges, test-programs and oscilloscopes. *)
> > The result (after some rework) you can now download as version 0.26
> >
> > The following items have been fixed/updated:
> >
> > - Reading from SID chip now implemented. (emulated registers removed)
> > - Fixed decimal mode of ARR instruction
> > - CPU speed changes together with the video mode if changed by
> > pressing F12.
> > - Fixed speed of dotclock and phi. System now runs at 0.9850Mhz for
> > PAL and 1.026Mhz for NTSC. Most floppy turbo loaders can now operate.
> > - VGA frame refresh rate now correct at 50Hz and 60Hz.
> > - Catridge port stability improved by adding data register that
> > buffers on read.
> >
> > As you can see many activities have been focused on getting the system
> > speed correct. Until now the C-One ran about 8% too fast. With this
> > update the system is within 0.5% of the real C64 speed allowing many
> > floppy speeders to operate.
> >
> > The ARR opcode and SID reading fix should satisfy a few extra programs
> > out there.
> >
> > Again sorry for the long delay between the last update. I was working
> > on other projects. I have only 2 hands, 1 brain and 1 kitchen table.
> >
> > The download file 'fpga64_026.zip' is available on my homepage at
> > http://www.syntiac.com/c_one.html <http://www.syntiac.com/c_one.html>
> >
> > or for a complete overview including older versions and test reports
> > see: http://www.syntiac.com/fpga64.html
> > <http://www.syntiac.com/fpga64.html>
> >
> > Don't let the bits byte you,
> > Peter
> >
> > *) No 8 bit home computers where damaged or harmed while developing
> > this core version!
> >
> >
>