I'd love to see the Chameleon multiplexer. :) (see email address if
you are feeling pity on me)

My biggest problem was that I didn't know to call it Multiplexer...
now that I do... Google is my friend. :)

I know that it might not be effecent, but would the megafunctions
lpm_mux and lpm_decode work?

It would seem to... but I'm still trying to find documentation
examples of them being used since I'm getting confused by the lpm_mux
having a sel(5..0) line that I don't understand. But that's what the
altera forum is good for i guess.

-Blair


2009/7/2 Peter <pwsoft@...>:
>
> Hoi Blair,
>
> --- In cone_cores@yahoogroups.com, "blairc64@..." <blairc64@...> wrote:
>>
>> Well... I've mastered using two FPGA's together in the same core from my own
code.  But as people are aware, there are limited pins to do this.
>
> Yes, only 8 between 1k100 and 1k30 and only 16 between extender and 1k30 (not
counting the 8 mdb lines as these are very slow).
>
> At least one thing I want to mention is that there is normally enough logic
available in the cyclone on the extender board. So the 1k30/1k100 are just there
for doing I/O. This reduces the required bandwidth quite a bit. You are not
really required to split the design in two (unless you want to do something that
runs on just the base PCB and the 1k100 is too small)
>
>>
>> For simple code or purpose writen code that easy.  You design the darn thing
with it in mind.  But now that I'm looking at porting code... I've come to the
issue... how to bridge two or more FPGAs with limited interconnection.
>>
>> Has anyone found a good simple way?  OpenCore "Bridge" or something?
>
> The trick is called time multiplexing. The gbridge is an example of this. I've
written my own multiplexer logic for the Chameleon core.
> What you do is send your data in multiple clocks and use something to
synchronise the start point (you could dedicate one pin for that, but there are
other ways).
>
> So for 4 bits you send D3, D2, D1, D0 on first clock, D7, D6, D5, D4 on the
second and D11 to D5 on the third and so on until you have send all the data
lines. Then addresses etc. Ofcourse the speed is lower, but the 1k30 and
extender can communicate upto about 100 Mhz reliably. So lets say you use 8
lines and need 40 bits you can still do 20M transfers per second on the shared
bus.
>
> Important is to send data only one way on a pin. So split the pins in half and
use one half for transfers from the 1k30 to extender and the other half from the
extender to 1k30. Although FPGAs pins can be bi-directional the switching of
directions will give you headaches. As many pins are input only on the extender
you are limited in the choice which pins are which direction. You also lose one
pin to transfer the clock. The 1k30 and 1k100 both already share a clock so here
all 8 gb lines are available for data.
>
>>
>> Mostly I'm interested in bridging wishbone code since that's what most people
seem to be using right now. :(  (seems like a waste of lines myself... but I
guess it makes things easy to code)
>
> Use something simple. Just a counter with a case statement running around and
around (but keep in mind you need a way to synchronise the starting point)
>
>> What have others looked at or found to help with bridging ports?
>
> There is also the same technique is used for the minimig port. It is used to
tranfer joystick, keyboard and IDE over just 16 lines.
> I've no problem sharing my Chameleon multiplexer, but it might not fit exactly
what you need, and might be better off with writing your own specific for your
needs.
>
> Peter
>
>>
>> -Blair
>>
>
>
>
>
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