At 13:41 01.05.2007 +0000, sixofdloc wrote:

>Aye, that would be useful. Is it already up somewhere?

The pinout of the CPU slot is on the web page,
but that does not tell you exactly how the CPU/RAM card is wired.

Unfortunately, I lost the CAD data of the CPU/RAM
card in a harddrive crash in february 2006, so I
had to reverse-engineer my own CPU/RAM card.
Wasn't too hard, as most of the CPU pins are
identical to the onboard CPU socket. The whole
secret was how I was planning to control the memory when I made that thing.

The lines MX, VPA and VDA of the 65816 are not
available. This does not hurt at all, because
they are not doing anything important (at least
nothing that you can't do with intelligent FPGA
programming). All other CPU lines are connected like in the schematics.

VDA/VPA: This pair of lines gives information
about the type of access. Since the C-One wants
to be as C64 compatible as it's possible with the
65816, there's no need to make a difference
between program/data/opcode fetch addresses. One
thing you can't see is if the cycle is idle, but
that shouldn't hurt, as the 6502 also makes idle
read accesses without a possibility to identify them on the outside.

MX: Memory index/Select status. This is an output
line from the processor that reflects two bits of
the status register (multiplexed with Phi2). We don't need that.

The MX line is not used on the CPU/RAM card at all.

The VDA line is connected to the CE line of the
128K S-Ram (this is 1k100 pin no. 109)
The VPA line is connected to address line A16 of
the 128K S-Ram (this is 1k100 pin no. 202)
The RW line of the processor is connected to the
WE line of the 128K S-Ram (this is 1k100 pin no. 206)
The OE line of the S-Ram is grounded.

Here's the idea of how the 65816 can be embedded
into the C-One without bigger problems:

The BE line tri-states the address bus, the data
bus and the WE line. BE=1 means that the CPU has
control, BE=0 means that the FPGA has control.
The BE line is on pin 208 of the 1k100.

The big difference between the 6510 and the 65816
is that the data bus is *always* driven during
Phi2=0 - the 65816 is transferring the bank
address during this cycle, and you might want to
get the bank address as well - this will require
a slightly different (sub-cycle) timing than in
the original C64. Nothing fancy, just inserting
the VIC cycle at a slightly different position within a cycle.

In case you're worried about the OE line of the
128K S-Ram grounded, that's the perfect way of
saving an IO line. Both a read and a write cycle
can be CE-controlled. Make sure to release the CE
line slightly before the end of a PHI cycle for a
write access, and slightly later for a read
access from memory so you meet the CPU's data hold requirements.

I have drawn two full PHI cycles with interleaved
VIC (FPGA) cycles: They're 1MHz only and
interleave VIC (FPGA) cycles with CPU cycles. VIC
cycles are always read, CPU cycles can be both,
therefore one is a read, the other a write
access. Three things that you should should mind
(look for stars in the sketch):
http://c64upgra.de/c-one/pics/65816_cone.jpg
(doesn't look nice, but you'll ge the idea)

*1: Push the RW line high before you pull the
ram-CE line low for the VIC read access.
*2: Hold ram-CE low slightly longer than the
falling edge of the PHI clock (PHI clock is pin 163 of the 1k100)
*3: on a write cycle, end the enable for the ram
slightly before the end of a PHI cycle to be safe from data transitions.

My guess would be that the overloaded C-One
data/address bus can make maybe 8MHz. That would
mean reliable 7MHz operation of the 65816
(slightly less with badlines). With two VIC/FPGA
cycles, you would still have 6MHz operation
during a badline. Better than Flash8!

Remember to give the data bus drivers of the FPGA
and the CPU enough time to enable/disable. You
cannot use the inverted BA signal in your 1k100
to enable/disable the local bus drivers. You
*must* generate a completely new signal that has
no corresponding edge (negative overlap) - leave
at least 10ns turnaround time (one 100MHz cycle).

good night,
--
Jens Schönfeld