The CS8412 is used in DIY, budget, and high-end DACs. The chip is long
out of production but DACs that use it are still being made. So, what
can be used as a substitute or upgrade? A popular choice is the
pin-compatible CS8414 mounted on a SOIC-to-DIP adapter but the CS8414
is also out of production and getting hard to find.

http://internet.cybermesa.com/~jmlpartners/images/dir6a.jpg

I made this widget that uses a CS8415A (mounted on the underside of
the PCB) operating like a CS8412 in mode 6. It is plug-in replacement
for a CS8412-CP and makes a nice upgrade for most Audio Note and
similar DACs. Other CS8412 operation modes can also be provided with
minor circuit changes.

http://internet.cybermesa.com/~jmlpartners/images/dir6a.png

The 24-bit, right-justified output of the CS8415A is shifted right six
bits yielding 18-bit samples. The CS8415A is a definite improvement
over the CS8412 and shifting one or two additional bits reduces the
DAC's settling time and that yields even greater clarity and dynamics.
Like jitter, settling is a period of time when the DAC is outputting
the wrong value during the transition to the next sample, except
jitter is measured in picoseconds and settling time is measured in
nanoseconds: a thousand times larger.

The oscillograph below shows the output of a Lite DAC-AH and the
difference between settling time and jitter. The falling edge of WS
(red) initiates the digital -to-analog conversion. The analog output
changes on the next rising edge of SCLK (violet). The right and left
channel analog output (green and yellow) begins changing after the
rising edge of SCLK but it takes a long time for them to reach the
final signal level for that sample period.

http://internet.cybermesa.com/~jmlpartners/images/dir6a_01.png

Near the left edge of the oscillograph are two orange, dashed,
vertical lines. One marks the trigger point, which is the rising edge
of SCLK, and the other marks 200 picoseconds after the trigger. (The
two lines are superimposed because the time interval is less than the
width of a pixel on the 'scope display.) 200 picoseconds is the
maximum RMS clock jitter spec for the CS8412.

As seen below, while the DAC's analog output is settling, the signal
is unpredictable and may include under-shoot, over-shoot, and oscillation.

http://internet.cybermesa.com/~jmlpartners/images/dir6a_02.png

Settling time is a function of step size. Right-shifting the sample
data one or two bits reduces the RMS step size by a factor of two or
four, respectively. The two oscillographs below show the composite
output of the same DAC. The orange cursor lines are at the trigger
point (rising edge of SCLK) and when the output signal appears to have
settled. The first oscillograph is of the unaltered test data. The
second is the same data right shifted one bit and amplified to the
same scale as the first.

http://internet.cybermesa.com/~jmlpartners/images/dir6a_07.png

http://internet.cybermesa.com/~jmlpartners/images/dir6a_08.png

DACs with marginal linearity also benefit from right-shifted samples.
In the oscillograph below, the green trace shows a full-scale 20Hz
sine wave; the yellow trace is the same signal shifted right one bit
and amplified to the same scale. The distortion evident in the
full-scale signal is absent from the shifted signal.

http://internet.cybermesa.com/~jmlpartners/images/dir6a_09.png

The settling behavior of different DACs varies widely and makes a
significant contribution to their unique sound qualities. I believe
the differences you hear between different DAC chips are mostly due to
their settling characteristics.