"Jan Gray" <jsgray@...> wrote:
> Each and every one of those transistors test out "perfectly" at the
> factory. I understand that the tester downloads a number of
> configuration bitstreams that fully exercise and cover the configuration
^^^^^
> memory, the CLBs, interconnect, etc.

Dream on... :-)

http://groups.google.com/groups?hl=en&th=4e7ce1c83a7baa68&seekm=20010731.103308.\
1239036029.24248%40polybus.com

> (((Wacky idea: I understand that testers step over each die on the
> unsawn wafer, pressing probe wires to the die's pads, powering it up,
> and running some test circuits. I wonder, is it practical to add power,
> ground, and JTAG-like test paths, between dice, to interconnect the dice
> on the unsawn wafer and thereby test entire wafers in parallel?

But there may be flaws anywhere on the wafer; actually some parts of
the wafer are quite likely to be non-functional. Anything in a
JTAG-like chain behind some non-functional part cannot be observed...
So you have to be able to route around flaws with unpredictable
locations and with uncertain distribution. That's quite a bit more
involved than a JTAG chain.

Worse, you'll have to get functional interconnect across the entire
wafer somehow. This is tricky with a wafer stepper (i.e. most modern
fabs expose wafers only one die at a time, and aren't set up to
produce working circuits between those dies). I know it has been
done with wafer steppers, but requires alignment between the steps
and support for funny design rules; expect it to come at a cost...

- Reinoud