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Emulation of Processor   Message List  
Reply Message #1784 of 3364 |
Re: Emulation of Processor

> Say I want to build a cycle accurate model of an exisiting
processor. Say Intel 386 for example. Now I have access to all the
data sheets and plenty of other information. Now I have, a very good
specifications as well a brief internal design.
>
> How exactly I go about handling this project, so that I make best
use of the all the information available and in very systematic way.

I have put together a cycle-accurate implementation of the 6502
processor. Whether this is a good appraoch to use or not, this how I
accomplished the task:

First, ignore the cycle accuracy. I'm of the opinion it's better to
get a working processor first, then make it cycle accurate. But keep
the cycle accuracy in the back of your mind. In other words don't put
together a bit-serial implementation of a byte wide processor, a
micro-code version of a RISC cpu, etc. The required conversion later
will probably only cause problems. My advice is to follow a similar
design pattern to begin with. Once you have a working processor, then
go back and patch it up so it's cycle accurate.

Get to cycle accuracy in stages. First try and make the cpu *faster*
than cycle accurate while keeping it simple at the same time. Once
it's faster than the original, it's easier to go back and add in
additional 'nop' cycles to slow the instructions down so they match
the original timing. Reducing the speed of a design is probably a lot
easier than trying to increase the speed of a design that started off
on the wrong foot with the wrong architecture.

Keep the pipelining of the original in mind. If the original
processor is pipelined so that instructions execute in a single
cycle, then you'll have to duplicate that pipelining in order to get
the single cycle instruction execution.

Tackle cycle accuracy on the instructions that are a) easy to make
cycle accurate, and b) the instructions that are likely to be the
critical ones for cycle accuracy. It might be acceptable for other
less critical instructions to be non-cycle accurate.

Cycle accuracy is mostly marketing hype. It's great to be able to say
the processor is 100% cycle-accurate, but it's not normally a
requirement. Coding that depends on cycle accuracy is strongly
discouraged because different versions of a processor (even within
the same generation from the same manufacturer) could potentially
have different timings. With todays complex systems involving
overlapped instructions sequences, caches accesses, interrupts, etc.
Almost no-one depends on cycle accuracy because it's an unreliable
approach.

Where cycle accuracy has been used in the past is for simple systems
where clock cycles were counted to determine timing delays. Most of
these delays consist of loops that simply decrement a counter. So
critical instructions to make cycle accurate are probably branch /
loop instructions and decrements / increments.

For my '02 implementation, in the first pass I had many instructions
that took longer than the original. Once I had the processor
basically working, I then looked at how I could streamline the cpu. I
streamlined the cpu to reduce all the instructions to the minimum
number of cycle (once again not trying too hard to keep cycle
accuracy). This was the second iteration of the cpu. At this point I
had all instructions executing in the same or fewer clock cycles than
the original. For the third iteration of the processor, I went back
and added in additional 'nop' cycles to extend instruction out to the
same timings as the original.

Note there are different kinds of cycle accuracy as well. My '02 has
instruction timing accuracy, but not bus-cycle by bus-cycle accuracy
(although it's very close).

Note obtaining cycle accuracy cost about 10% of the clock cycle, and
10% in size. The cycle accurate version runs at 10% slower clock
frequency and consumes about 10% more fpga resources. (Cycle-accuracy
uses the fpga resources less efficiently than they could otherwise be
used in this case). I have an option to build the code with non-cycle
accuracy for better performance and size.

=================================================

I spent about a year getting the 02 basically working. It was more
than another year before I had it cycle accurate. These were not
really man years, but I spent a lot of time at it on weekends and
evenings. It' probably represents many man-months of effort anyway (I
can code and get things working very fast....)

The x86 series is a complex processor. Twice I've started a 8086
clone, but then dropped it after a just a few hours. I'd estimate it
to be about three or four times more complex than the '02, meaning it
would probably take me about five years to get a decently working
version (without working on it full time). Something like the 386 is
several times more complex than that so the other poster's comment
about spending 30 man years isn't an unreasonable time estimate.
still, if you like a
challenge.....


Implementing an existing processor has a lot of attraction because of
the existing base of software and tools.

Depending what your goals are...... it might be easier to get x386
comparable performance with a much simpler processor. For instance
isn't the xr16 20 MIPS ?


Rob








Sun Dec 21, 2003 5:20 am

rtfinch36
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Message #1784 of 3364 |
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Hi All, Say I want to build a cycle accurate model of an exisiting processor. Say Intel 386 for example. Now I have access to all the data sheets and plenty of...
Anand Gopal Shirahatti
anandg_s@... Send Email
Dec 18, 2003
4:59 am

When you say emulation, do you mean in FPGA (as per list) or are you thinking about a software emulation? ... From: Anand Gopal Shirahatti...
veronica.merryfield@...
veronica_mer... Offline Send Email
Dec 18, 2003
6:25 am

... I ... that ... That is a very good question. The answer obviously depends on level of seriousness (commercial, research, hobby) and degree of accurateness...
Tommy Thorn
tt1729 Offline Send Email
Dec 18, 2003
6:30 am

Ofcourse on FPGA ! Final goal is VHDL RTL ... [Non-text portions of this message have been removed]...
Anand Gopal Shirahatti
anandg_s@... Send Email
Dec 18, 2003
6:51 am

... [...] ... With all due respect, you're in way over your head. The 386 is one of the most complex scalar processors ever. Start with something simpler. If...
Eric Smith
jdripper Offline Send Email
Dec 19, 2003
3:07 am

... The 386 is one of ... something simpler. ... But you'd be better ... The stuff you learn ... ready to tackle ... I don't even know how to start replying to...
Tommy Thorn
tt1729 Offline Send Email
Dec 19, 2003
5:15 am

... I have no idea who Ananard is. I don't know Anand Gopal Shirahatti, but I do know that it takes more than thirty man-years for a team of expert...
Eric Smith
jdripper Offline Send Email
Dec 20, 2003
4:25 am

... processor. Say Intel 386 for example. Now I have access to all the data sheets and plenty of other information. Now I have, a very good specifications as...
Rob Finch
rtfinch36 Offline Send Email
Dec 21, 2003
5:20 am

Hi Rob, May i ask for more information on how you implement the 6502? cos i am doing an emulator on 6502 also .... I plan to emulate the 6502 by Verilog .... ...
Eng How Khoo
enghow1268 Offline Send Email
Dec 22, 2003
3:34 am

... Hi, About testing Verilog cores... I'm working currently on bridge from Verilog simulator to Java (using VPI). It is in early stage now and supports Linux...
Tomasz Sztejka
sztejkat Offline Send Email
Dec 22, 2003
6:53 am

Hi Tomasz Sztejka, Can explain more about the bridge .... what is a bridge? The simulator will onli work in Linux environment? How about window? cos most of...
Eng How Khoo
enghow1268 Offline Send Email
Dec 22, 2003
10:06 am

... The Icarus Verilog (http://icarus.com/eda/verilog/) is a free Linux/Windows/etc verilog compiler plus simulator (this is Verilog chip description language...
Tomasz Sztejka
sztejkat Offline Send Email
Dec 22, 2003
8:11 pm
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