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VHDL syntax question   Message List  
Reply | Forward Message #1669 of 1767 |
Re: VHDL syntax question

Alright then. I am having an issue with the UCF file. I am getting an error
message which says:

ERROR:MapLib:30 - LOC constraint R18 on sram_addr<21> is invalid: No such site
ERROR:MapLib:30 - LOC constraint R16 on sram_addr<22> is invalid: No such site
ERROR:MapLib:30 - LOC constraint P18 on sram_mode is invalid: No such site on

I was thinking it might be related to IOSTANDARD, DRIVE, SLEW statements but
that seems highly unlikely. So far, I have filed a web case with Xilinx. I am
using the full version of ISE 10.1 so it shouldn't be puking due to an
unsupported device. I have triple checked to make sure that I have the correct
target (the ML405 board) targeted in the project. No syntax errors found in the
ucf file either. I'm at a bit of a loss here.

Any ideas? Thanks.

--- In java-processor@yahoogroups.com, "Martin Schoeberl" <martin@...> wrote:
>
> Slew rate is the time a signal needs to change the logic level. If your
> external device has a tight timing (e.g. SRAM) a high slew rate helps.
> For less critical interfaces a slower slew rate reduces electrical
> radiation and noise.
>
> Martin
> ----- Original Message -----
> From: "dslaman0877" <dslaman0877@...>
> To: <java-processor@yahoogroups.com>
> Sent: Monday, July 06, 2009 4:59 PM
> Subject: [java-processor] VHDL syntax question
>
>
> > I've modified the UCF file of the ML401 to port over to the ML405. One
confusing part in the ML401 UCF is starting at line 100
> > and on, there are descriptions added to the memory interface and I don't
understand what they are there for. E.G. -->
> >
> > NET sram_clk IOSTANDARD = LVCMOS33;
> > NET sram_clk DRIVE = 16;
> > NET sram_clk SLEW = FAST;
> >
> > I understand what the SLEW = FAST means, but I don't know what it is there
for. Can anybody tell me what all this means? Thanks
> > in advance.
> >
> >
> >
> > ------------------------------------
> >
> > Yahoo! Groups Links
> >
> >
> >
> >
>





Mon Jul 6, 2009 4:11 pm

dslaman0877
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Forward
Message #1669 of 1767 |
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I've modified the UCF file of the ML401 to port over to the ML405. One confusing part in the ML401 UCF is starting at line 100 and on, there are descriptions...
dslaman0877
Offline Send Email
Jul 6, 2009
2:59 pm

Slew rate is the time a signal needs to change the logic level. If your external device has a tight timing (e.g. SRAM) a high slew rate helps. For less...
Martin Schoeberl
jopdesign
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Jul 6, 2009
3:44 pm

Alright then. I am having an issue with the UCF file. I am getting an error message which says: ERROR:MapLib:30 - LOC constraint R18 on sram_addr<21> is...
dslaman0877
Offline Send Email
Jul 6, 2009
4:12 pm

This is pretty bad, I'm replying to myself. I figured out the problem is that Xilinxs website provides an ML405 schematic for the board with an FX60 onboard,...
dslaman0877
Offline Send Email
Jul 9, 2009
7:59 pm

Hello! I tested jop on ml405...
Oleg Belousov
strijar
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Jul 9, 2009
9:22 pm

... Thnaks!...
dslaman0877
Offline Send Email
Jul 9, 2009
11:30 pm
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