Dear Collegues: I am a very experienced software developer and systmes architect, but I'm a complete newbie with FPGAs, and I have forgotten what I knew from...
I found the the initial problem. the makefile uses semicolons to separate the files in the classpath. This does not work on Linux. replacing all "\;" with ":"...
Colleagues: The User reference describes the process fro using JOP, to include make tools This fails on Linux systems, as described in earlier posts to the ...
Hello Martin, I have spent the last 4 weeks simulating and testing the wishbone compliant DDR SDRAM interface that we discussed last month. Several subtle...
Dan, ... Thank's for pointing this out! Is it really just the ':' seperator and the Makefile works under Linux? That's good news. BTW: there is another way to...
... mmh, I don't think this will be an issue for just a few days :-( The spartan s3e sk has a DDR SDRAM as memory and there is no such controller available in...
Hello Marlon, ... ok good to hear. ... I'm not sure if I understand your configuration correctly. The UART that receives the program normally is connected to...
(Please forward this note to any colleagues who you think may be interested. Please reply to me If you would like your name removed from this mailing list.) ...
Thanks Martin, ... ModelSim ... Interesting. That explains why I could never trace the program data from rx to the core for execution (when simulating with...
... ok, keep us posted about your progress. ... That triggeres an idea about the issue: How to you enforce that JOP waits till the initialization is done? At...
... [I wrote] ... I found other comments about this on the web, and was about to get discouraged when I found a solution by David Ashley on a forum: ...
... I modified the top level of JOP slightly. The process for the internal reset was modified to include a reset, in addition to clk. As a result, an...
... This sounds very similar to what I am trying to do on the Virtex board. Please keep us posted with your progress. I will be glad to assist you any way...
... I would keep the original counter thing and just add ... change to: int_res <= not res_cnt(0) or not res_cnt(1) or not res_cnt(2) or rst. ... In that case...
... yes, looks like a non trivial thing. That's why I don't like DDR SDRAM. I hope simple SDRAM will be a little easier. At least for Altera there is a free IP...
Hi, i'm FPGA expert but JAVA newbie. I want to use JOP as VHDL testbench for the opencore wishbone I2C Master. I followed the Spartan3 description in the...
... Looks like a CLASSPATH setting issue. Try to remove any pathes in CLASSPATH so the JOP JDK is used for the System class instead of the JDK installed on...
I can't find the CLASSPATH variable. I found following JAVA dependencies: JAVAHOME='C:\Program Files\Java\jdk1.6.0_03\bin' PATH='/cygdrive/c/Program...
no, CLASSPATH should not be set. So you're running javac from within Cygwin? I usually do it from the Windows CMD box. However, just tried the make from the...
... Hello Marting, I connected the rst signal to the core as you suggested. Still getting the same result. I also used the jopser.bat to generate the...
Colleagues: I finally managed to build the DDR interface code and its test driver on my Gentoo Linux system and download it to my Spartan 3E board. The ...
... Great news ! Please keep us updated. Which board are you using the e500 or the e1600 version ? cheers...
emu@...
Jan 10, 2008 9:14 am
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Hi Martin, Firstly, Happy New Year! Thanks for that information - although I'm not sure my changes are actually having an effect as my ModelSim license is...
Hi Chris, ... that's not so bad as the .jop file is very verbose. At the end of the JOPizer run you see a message on the actual program size. ... JopSim...
Hi Martin, I've changed a few things only to have a re-occurring problem in changing this for my application. It is definitely in Const.java where I change to...
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