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Messages 1650 - 1680 of 1784   Oldest  |  < Older  |  Newer >  |  Newest
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1650
Martin, Thanks for your reply but I think that this job is not exactly what I want ! I want to use jdb for trace jop execution (breakpoint, step, list,...
Rodolfo Galvão
rodolfogalva...
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Jun 1, 2009
2:54 pm
1651
Ok, but when jdb uses JDWP than that is one way to accomplish your task. Why not using the work that Paulo has already been done? Anyway, an additional JTAG...
Martin Schoeberl
jopdesign
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Jun 1, 2009
4:26 pm
1652
Hi Martin, JOPers, I've replaced all the core files in my design as it would seem that I have been using a JOP release from Jan '08 - which is quite old. I've ...
c.p.bridges@...
cpbridges_ssc
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Jun 2, 2009
4:07 pm
1653
Hi Chris, ... ok, fine. ... What do you mean with "stack not set"? On my plain simulation (single JOP with 100 MHz) till 1 us there are sporadic reads (reading...
Martin Schoeberl
jopdesign
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Jun 3, 2009
1:00 pm
1654
Hi Martin, Thanks for the reply. That 'stack not set' is the sporadic reads you mention. I am using the old one still at the moment to get around the ...
c.p.bridges@...
cpbridges_ssc
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Jun 3, 2009
1:37 pm
1655
Martin, As I understand, for debbug a code running in JOP I must run, in addition to the application, another sw that will connect do the debug server in PC?...
Rodolfo Galvão
rodolfogalva...
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Jun 6, 2009
1:24 pm
1656
====================================================================== CALL FOR PAPERS The 7th Workshop on Java Technologies for Real-Time and Embedded Systems...
Martin Schoeberl
jopdesign
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Jun 7, 2009
6:21 pm
1657
Hi JOP'ers, With regards to the exception handling and interrupts, what do the irq_in signals do exactly? In my design with the LEON3, I have no handling of...
c.p.bridges@...
cpbridges_ssc
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Jun 15, 2009
2:14 pm
1658
... If you do not use interrupts, you can leave the irq_in signals unconnected. That's the case for a 'standard' JOP configuration. They have a default value. ...
Martin Schoeberl
jopdesign
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Jun 16, 2009
8:10 am
1659
Hi Martin, That's what I currently have at the moment but I wanted to make it more robust. Can you tell me what the irq_in signals do exactly? I've read the...
c.p.bridges@...
cpbridges_ssc
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Jun 16, 2009
10:30 am
1660
Hi Martin, JOP'ers, I've successfully got a working JOP as an AHB Master but I have some odd results on the stack. Only tos is used and not nos. See: ...
c.p.bridges@...
cpbridges_ssc
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Jun 17, 2009
11:48 am
1661
... irq_in are for I/O devices that want to use interrupts. If you don't have such a device, just keep them open. ... mmh, I don't understand your question....
Martin Schoeberl
jopdesign
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Jun 17, 2009
10:13 pm
1662
... mmh, AFAI can tell the diagram does not look so bad. NOS is getting a value after some time. That's fine as TOS and NOS are undefined at start. Martin...
Martin Schoeberl
jopdesign
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Jun 17, 2009
10:18 pm
1663
I am trying to get the JOP onto the Xilinx ML405 board. I am using Xilinx ISE 10.1. First, the UCF file. I went into the JOP folder (downloaded from...
dslaman0877
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Jul 2, 2009
3:02 pm
1664
... Why are you starting with quartus ? There is a ML401 project already, so I would guess that's a better start. cheers...
emu@...
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Jul 2, 2009
3:13 pm
1665
... Oops, missed that. Thanks....
dslaman0877
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Jul 2, 2009
4:32 pm
1667
I've modified the UCF file of the ML401 to port over to the ML405. One confusing part in the ML401 UCF is starting at line 100 and on, there are descriptions...
dslaman0877
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Jul 6, 2009
2:59 pm
1668
Slew rate is the time a signal needs to change the logic level. If your external device has a tight timing (e.g. SRAM) a high slew rate helps. For less...
Martin Schoeberl
jopdesign
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Jul 6, 2009
3:44 pm
1669
Alright then. I am having an issue with the UCF file. I am getting an error message which says: ERROR:MapLib:30 - LOC constraint R18 on sram_addr<21> is...
dslaman0877
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Jul 6, 2009
4:12 pm
1670
This is pretty bad, I'm replying to myself. I figured out the problem is that Xilinxs website provides an ML405 schematic for the board with an FX60 onboard,...
dslaman0877
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Jul 9, 2009
7:59 pm
1671
Hello! I tested jop on ml405...
Oleg Belousov
strijar
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Jul 9, 2009
9:22 pm
1672
1. I made an assumption when creating the JOP project within Xilinx ISE 10.1. When I open the .npl file, there is a list of project files - so I went through...
dslaman0877
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Jul 9, 2009
11:03 pm
1673
... Thnaks!...
dslaman0877
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Jul 9, 2009
11:30 pm
1674
Hi Everyone, I was wondering if there were any results for JOP running Seive and Lift? Cheers, Chris...
cpbridges_ssc
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Jul 10, 2009
10:27 am
1675
... Ignore those errors as they are commands for the Altera build process. After that run the Xilinx bitfile generation and configure the FPGA. That should...
Martin Schoeberl
jopdesign
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Jul 10, 2009
10:24 pm
1676
I'm using Xilinx ISE 10.1 I performed a fresh checkout of the JOP (I'm attempting to get it working on a Xilinx ML405 board with FX20 onboard). I open ISE,...
dslaman0877
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Jul 10, 2009
11:50 pm
1677
Hello. Itself create a new project...
Oleg Belousov
strijar
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Jul 11, 2009
7:49 am
1678
... That's strange. I just did a clean checkout, run make tools, make jopser - stoped on the quartus call and opened the jop.npl in Xilinx ISE (9.2). It...
Martin Schoeberl
jopdesign
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Jul 11, 2009
8:32 am
1679
... The latest numbers on Lift are in following paper: @ARTICLE{tpca:jes, author = {Martin Schoeberl}, title = {Time-predictable Computer Architecture}, ...
Martin Schoeberl
jopdesign
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Jul 11, 2009
9:02 am
1680
... Well, since it apparently doesn't want to work as it should - how about this idea. If I open the jop.npl file in a text document, I see this: JDF H //...
dslaman0877
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Jul 11, 2009
7:28 pm
Messages 1650 - 1680 of 1784   Oldest  |  < Older  |  Newer >  |  Newest
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