Hi, has anybody ever ported JOP to Virtex 800? Actually, I work with XSV800 (Xess) board which has one Virtex 800 FPGA Device. Any help will be wellcome ...
Martin: In putting together a basic kernel of JNode, I noted that there is no Wishbone bus driver. Before embarking on putting together a driver, I noted that...
... I don't think you need a driver for the Wishbone interface. Wishbone is just a hardware bus specification. In the case of JOP you access the Wishbone...
This is useful info. ... So after reading this, I think you should skip all of the JNode JVM code, since it is not needed anymore. This does however mean that...
Hi, I have spent several days trying to change mem_xs3.vhd for spartan 3. Instead of using this (in mem_xs3.vhd file): -- the block ram is 2KB instead of 1KB! ...
Hi Marcos, good to hear that someone is adapting the (new) cache to the Spartan-3 version. The cache is allready implemented in the Cycylone version. Perhaps...
Hi, Thanks. Just for your information, I work with thesis version of JOP cause, although I will need wishbone, up to now is the easiest version to be ported. I...
I got it wrong in the first place. You are trying to just substitute the RAMB16_S9_S36 by the ramb16s9s36 component and not implement the new cache design. And...
Thanks, I was wrong. Now it`s working for spartan 3 starter kit. The purpose of this change in the cache is because I'm trying to port JOP to virtex xcv800....
Hi, In your papers, several times the flexibility with the FPGA is mentioned (regarding HW/SW co-design), i.e. that some functionality can be implemented...
Hi Mads I hope Martin doesn't mind my giving a rather general answer to this =) ... There are a couple of ways to accelerate JOP with hardware. - You could add...
... Yes, bytecode 196 (wide) is currently not implemented. 'wide' is usually not used for normal sized applications. However, some (1.5?, Eclipse) Java ...
Hi Rapael, jdk 1.5 is not tested with JOP. You can try to play around with the compiler flags (-target) or use jdk 1.4 Martin ... From: "Ponsard Raphael"...
Hi group, I've built an IO board [1] for an FPGA module to be used in a DSP lab at the university. The idea is to use USB for powering the board, transfer data...
Hello I am trying to assemble the jvm.asm file following the step of the "Getting Started" but for some reason it doesn't work properly Can someone help me ? ...
Hi, I'm trying to run JOP on a spartan 3 starter kit. Can someone tell me on which version of ISE the project was created. I tried 7.1 (non SP) and 6.1. 6.1...
I have used 7.1 with no problems. I have not tried it with the latest JOP release but I have had success with 7.1 but I had the SP installed. If trying...
One other thing to note with 7.1 is that if there is any spaces in the path to the project or any of its files such as c:\my documents\jop it will have a...
Well I took soemtime to test the latest JOP in ise 7.1 and I had no issues building the file or anything here. Your ISE instalation is either corrupt or there...
Hi Ezequiel, first you need a platform for JOP, i.e. a FPGA board with some external memmory. JOP runns out of the box on three FPGA boards: The Cyclone CYCORE...
Hello Is there any chance that I can make this boards, or all of them are sold by a manufacturer and they doesn't give PCB or Schematic? Thanks Ezequiel 4 Oct...
The schematic is available for the boards, but not the PCB. If you need a free FPGA board design you can take a look at http://www.opencores.org/. For the ACEX...
Making an FPGA board takes time you can get the schematic but the designing and manufacturing then soldering ansd testing all these things get timne instead...
Hi, You'd better buy spartan 3 starter kit (it's dirty cheap, really a bargain, from Digilent is cheaper than Xilinx) rather than any board with Virtex or...
I originally ported JOP to the Spartan II. I'm sure that the same techniques can be used to port it to the Spartan I, but it's probably not worth it. The...
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