The leon3 pipeline is deeper than leon2, to avoid using the negative
edge on the clock. This will allow leon3 to reach higher frequencies
compared to leon2.

Jiri.

gyuekjay wrote:
> --- In leon_sparc@yahoogroups.com, Jiri Gaisler <jiri@...> wrote:
>>
>> The best solution is to switch to leon3 (you are using leon2), which
>> does not use the inverted clock.
>>
>> Jiri.
>>
>> gyuekjay wrote:
>>> Hi,Gaisler Team,
>>> In tech_map.vhd,entity regfile_iu include a dpram with two clks that named
clk and clkn(clkn=not clk).
>>> When i did logic synthesis,the period of time path between clk and clkn is
half of the period of sysclk.So the time report have some violations.The tool is
DC 2002,and the library is slow of smic18.The period of sysclk is 7.6ns. I dont
know how to deal with this probrem, hope someone could give me some suggestions.
>>> Thank you very much!
>>>
>>>
>>>
>>> ------------------------------------
>>>
>>> Yahoo! Groups Links
>>>
>>>
>>>
>>>
>> The best solution is to switch to leon3 (you are using leon2), which
>> does not use the inverted clock.
> ---
> Hi,jiri,
> Thank you for your reply,but i dont know why the leon2 does not use the
inverted clock,in fact ,i find the module of proc use clk and clkn in
mcore.vhd,the module of regfile_iu in leon2 and leon3 include the dpram which
has two clk port,the difference between the leon2 and leon3 is:
>
> leon2->the two clk port connect to clk and clkn(mocre.proc.iu.regfile_iu ),and
if the two clk port both connect to clk,then the simulation will fail
> /*proc0 : proc port map (
> rst, clk, clkn, apbi(2), apbo(2), ahbmi(0), ahbmo(0),
> ahbsi(0), iui, iuo);*/
> ------------------------------------------------------------------
>
> leon3->the two clk port both connect to clk(leon3mp.leon3sh.regfile_3p),and
the simulation will pass
> /*-- IU register file
>
> rf0 : regfile_3p generic map (memtech, IRFBITS, 32,
syncram_2p_write_through(memtech), IREGNUM)
> port map (clk, rfi.waddr(IRFBITS-1 downto 0), rfi.wdata, rfi.wren,
clk, rfi.raddr1(IRFBITS-1 downto 0), rfi.ren1, rfo.data1,
> rfi.raddr2(IRFBITS-1 downto 0), rfi.ren2, rfo.data2, rfi.diag);*/
> --------------------------------------------------------------------
> The best solution is to switch to leon3 ,that is a good suggestion.
> But now i must insit on using leon2, i can use the inverted clock,but the
system frequency will be lower than using the clock,
> the leon3 only use a clock ,so the system frequency will be higher and the
logic synthesis will not have the problem which i have found in leon2,is right?
>
> Thank you very much!
>
>
>
>
>
> ------------------------------------
>
> Yahoo! Groups Links
>
>
>
>