I've got a similar question with a different board.
Any chance you know the proper LOCATE constraints for the xupv5 w/ the lx110t?
:)

--- In leon_sparc@yahoogroups.com, Jiri Gaisler <jiri@...> wrote:
>
>
> I have a new look at this - the correct LOCATE constraints
> for ML509 should be:
>
> INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl.0.u" LOC =
"IDELAYCTRL_X0Y1";
> INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl.1.u" LOC =
"IDELAYCTRL_X0Y2";
> INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl.2.u" LOC =
"IDELAYCTRL_X0Y6";
> INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl[0].u" LOC =
"IDELAYCTRL_X0Y1";
> INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl[1].u" LOC =
"IDELAYCTRL_X0Y2";
> INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl[2].u" LOC =
"IDELAYCTRL_X0Y6";
>
>
> Jiri.
>
> Jiri Gaisler wrote:
> > Yes, you need to change the LOCATE constraints for the IODELAYs.
> > ISE is unfortunately not smart enough to figure out where to
> > place them automatically ....
> >
> > Jiri.
> >
> > jamesloa wrote:
> >> I'm kinda confused about what needs to be changed in the ucf file. Is
> >> it the idelctrl constraints or something else?
> >> -Jim
> >>
> >> --- In leon_sparc@yahoogroups.com, Jiri Gaisler <jiri@> wrote:
> >>> The easiest way is probably to open up the ISE floorplanner
> >>> and check which IODELAY locations are closest to the DDR2
> >>> pads. Then change the .ucf with the corresponding locates
> >>> and you should be done ...
> >>>
> >>> Jiri.
> >>>
> >>> jamesloa wrote:
> >>>> I am currently trying to put the Leon3 design on ML509 board from
> >>>> Xilinx. Since this board is the same as the ML505 just with a larger
> >>>> FPGA I'm using the 505's design from grlib. I've generated a netlist
> >>>> in synplify and now I'm try to create a bitstream in XPS but I keep
> >>>> getting the following error:
> >>>> ERROR:Place:872 - Delay element
> >>>>
> >>
"iop_fpga_0/iop_fpga_0/leon3mp_0/ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/dd\
gen.43.del_dq0/IODELAY"
> >>>> has been placed at IODELAY_X0Y247 due to the following location
> >>>> constraint on component "iop_fpga_0_ddr_dq_pin<43>": COMP
> >>>> "iop_fpga_0_ddr_dq_pin<43>" LOCATE = SITE "P26" LEVEL 1
> >>>> However, the delay controller that calibrates this delay element
> >>>> has not been used. Please instantiate a delay controller and apply
> >>>> appropriate location constraint, or instantiate one delay controller
> >>>> for the design with out any location constraint. Please refer to the
> >>>> usage document to use the controller efficiently.
> >>>>
> >>>> Has anybody ever gotten the Leon3 on the 509 or does someone know what
> >>>> this error means? I read about changing the idelctrl locations in the
> >>>> ucf but this didn't seem to do anything. Thanks for any help you can
> >>>> offer.
> >>>>
> >>>> -Jim Anderson
> >>>>
> >>>>
> >>>> ------------------------------------
> >>>>
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> >>>>
> >>>>
> >>>>
> >>>>
> >>
> >>
> >> ------------------------------------
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