Hello,

after a long time of development, Daniel Bretz has finished his work with
Leon. I've put all my design files and the scripts on the web. My working
environment is SynopsysDC, Mentor ModelSIM, Xilinx Alliance 3.2i and as
prototyping board the XSV-800 from Xess with a Xilinx Virtex XCV800.

The files can be found at http://www.ra.informatik.uni-stuttgart.de/Leon/

There is also a port of the Xess command line tools to Linux. This version
supports the upload of exo-files, too.


There are still some questions left. Has anybody experience with loading
the Leon design from the FlashRAM to the FPGA? My programs sometimes fail
during startup process, when I use the the FlashRAM as boot ROM. The problem
occurs sometimes after reseting the CPU or after turning the power of the
board on, which leads to a new initialization of the FPGA.

Can anybody guess, if this is a design problem or a problem of the board?
Maybe somebody has seen the same problem before.


Another question is about the normal compile environment? I've recognized
that the dynamic memory allocation (malloc(), free()) and the using of
the library times (used by the dhrystone bench) don't work. Is this,
because there is no operating system under the static clib, or is this a bug?
How can I run the dhrystone benchmark?


greetings,
from Daniel Bretz

--
Rainer Dorsch
Abt. Rechnerarchitektur e-mail:rainer.dorsch@...
Uni Stuttgart Tel.: +49-711-7816-215 / Fax: +49-711-7816-288
Breitwiesenstr. 20-22 D-70565 Stuttgart