Hi all, I have some questions here. 1) what is the booting options available and how to configure it? 2) does SPARC v8 instructions are the exact instructions...
I'm not an expert here, but probably you won't get answer soon, because of the weekend... 1- Start by "grlib.doc", generally the processor will boot from a ROM...
Hi, I'm debugging apbpuart module of leon3. I found that writing APBUART control register(address 0x80000108) causes the program exit. the remain part of the...
Hi, Have you tried to simulate your application with the disas generic enabled so that you get an instruction trace and can see what is actually executed? ...
Can anyone look at these dmao and signals please? still getting incorrect read values. what are the common problems for an incorrect read (with a HRESP = 0)...
OK, it's probably best that I brief you on the C program first maybe. The C code is added to systest.c and will put data into an array and store it at...
Figured out the problem: I was calling a location that, in simulation, is an address in the prom.srec and not the sdram.srec. This is of course different to...
Hi everyone, I want to write a simple C program to do the following: the program has a counter (0-15) and this counter value is reflected on 4 LEDs in the...
Hi, I'm using grlib 1.0.21-b3848 on a leon3-gr-cpci-xc4v target. So far so good: For a realtime application with 2 leon cores I'm trying to use the fixed...
Philip Axer
axer@...
Nov 5, 2009 8:29 am
16487
Hi again, a small update on this: When trying to connect to the board ahbmo(2).hbusreq (uart debug) goes high. However cpu #0 keeps the busownership...
Philip Axer
axer@...
Nov 5, 2009 9:28 am
16488
Hi Philip, Have you checked that the number of AHB masters setting (nahbm) is correct and that there are no slots in ahbmo with undefined values? Best regards,...
Magnus Hjorth
mhjorth@...
Nov 5, 2009 10:01 am
16489
Hi, the described issue also affects an out-of-the-box setup (grlib 1.0.21-b3848). But to be sure I double checked the setting, and they seem to be ok. In my...
Philip Axer
axer@...
Nov 5, 2009 10:51 am
16490
It works here using the same grlib version as you use. Exactly what changes do you do to the unmodified grlib when synthesizing the system? How do you observe...
... That's weird! I just tested it again on a clean/unmodified version. Same issue. RRobin => works, Fixed Priority => broken ... Through the GUI I set: *...
Philip Axer
axer@...
Nov 6, 2009 11:30 am
16492
Ok, I thought you only had 4 masters enabled (2 x cpu, ahbuart, jtag) but if you only made those changes you mentioned then the GRETH, PCI MTF and CAN must ...
Hello, I writte this message, to see if is possible to add the correct delays for the altera pads to make a simulation with the DDR memory controller. In...
Hi Eljammali, first off, I assume you are using the sources provided by gaisler research as they are. Check the grgpio section in the grip manual and be sure...
Philip Axer
axer@...
Nov 6, 2009 7:28 pm
16496
Hi, In GUI window, I can see only a piece of the disassemble code. So how can I set breakpoint where I want? Thanks and regards!...
Hi, I have question about interrupt. according to the doc, IRQMP only use IRQ[15:0], so I consider that there is 16 interrupt numbers. But GPIO has at most 32...
... See the "Extended interrupts" section in the IRQMP documentation. If you want more interrupts you need to attach secondary interrupt controllers to IRQMP. ...
... In simulation it is probably easier to capture the complete output and then search for the address of the store that you suspect of doing something wrong....
Hello, Could you tell me if I need add a new technology to the library for the Xilinx SP3a-dsp FPGA, or I can just use spartan3 in my technology setting?...
I have followed the same procedure you used and it worked straight off with both ise 9.2 and 10.1 regardless of the arbitration setting. Are you using XST for...
Why can't I creat an application with the instruction area (-Ttext) between 0x1000000 and 0x3fffffff? The Leon i used has a flash memory on 0x10000000 bus and...
Now I have run the synthesis with XST as well and can verify that it is a XST problem. None of the debug links can access the design when fixed priority is...
Hi all, I hope you can help me. We are currently developing a system on an Atmel AT697E processor and have a requirement to be able to trap a data access...
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