Hi, so far I happily debugged using grmon and an attached sparc-elf-gdb. However now I have a failure happening on the second core in a multi-cpu leon3...
I have recently changed computer setups after my old computer died. I am using the same bitfiles and version of ISE, but I cannot connect to GRMON over...
Thank you for the quick reply. I have tried your suggestion, but have the same problem. When I make the gateway the same as the EDCL IP my network adapter says...
... Note that if you use unlinked object files you are creating a execute-in-rom image. Please reference the mkprom manual. You can use the "-v -dump" options...
Hi, I have realized that modelsim is needed to make vsim and mig_series7 operations. I was able to successfully make mig_series7 operation, since I have...
Yes exactly Jiri, ... Scanning libraries  grlib: stdlib util sparc modgen amba  secureip: ise  unisim: ise  synplify: sim  techmap: gencomp inferred...
Hello, I´ve programmed LEON3 on the Xilinx ML509 (Virtex5) board with the grlib.gpl-1.1.0-b4108 package (as I didn´t know how to do it with the most recent...
... You can not ping the EDCL, it only supports ARP and UDP packets. Make sure your network settings are OK by trying to ping an other computer on the network....
I have two Ethernet adapters in my computer, one that connects to a network and one that connects straight to the ML605. So I cannot ping anything when only...
after using chmod , make ise gives the following: make ise rm -rf xst xst -ifn leon3mp.xst Release 13.4 - xst O.87xd (lin64) Copyright (c) 1995-2011 Xilinx,...
Try to execute: source /opt/Xilinx/13.4/ISE_DS/settings64.sh in the shell before running 'make ise'. This is necessary to set up the Xilinx library paths. ...
Hi, i have written a monitoring module that is only responsible for reading PC of one the cores and do some analysis. I want to put it in the testbench and...
... Specify the files you need to compile in the template design's Makefile by adding them to VLOGSYNFILES or VHDLSYNFHILES (depending on if you have the...
... The mig_series7 target assumes ModelSim. For the next release we have also added support for Xilinx's simulators so there should be less trouble. If you...
Hi, ... OK. And the split generics of both AHBCTRL and SPIMCTRL are assigned? ... Yes, this could happen if you are connected over JTAG. Can you try performing...
I solved the clock issue with removing the leonbare_init_ticks() command. Now I have a wide range accurate 1MHz clock called with my clock() function......
Hi everyone, I have a question about the caches set size. Indead I used 8kB of instruction cache in 1 set, and it worked fine. I then wanted to increase this...
I'm making a system where I change hardware configuration at runtime with a kernel module. For certain bitfiles I get a "kernel illegal instruction". I'm not...
Hi everyone, it seems that I found my problem: it's in the memory_umc18.vhd. There is RAM implemented only to abits=11 and the error message only if abits is...
