Hi, While trying to compile snapgear-p33a the following errors occured: sparc-linux-gcc: /usr/src/SparcV8Linux/snapgear-p33a/lib/uClibc/lib/ crt1.o: No such...
Hi all, The leon3 processor is configured with the memory management unit (MMU) and the floating-point unit (FPU) enabled . If we want to write linux kernel...
Hello, I have used the default configuration for leon2 (without ethernet,pci) that I found in the config.vhd file. I synthesized the design in a Virtex2 (using...
The write strobe and data bus drivers are disabled on the same clock edge. On real hardware, the data is kept stable by the capacitance on the data lines which...
Dear Jiri and others, I'm trying to connect GRMON with the GR-CPCI-XC2V6000 development board via JTAG parallel cable, but there are still some problems, where...
hwulf@...
Sep 4, 2007 3:16 pm
11842
Hello, The JTAG debug link is apparently not enabled in your design. Use xconfig to enable it. Before you start the synthesis check that the JTAG debug link is...
Hi Jiri, I'm currently designing a Virtex-5 110/330 board that will host a Leon3 design. A question about the DDR sdram config: Suppose I want to populate the...
Thank you for your answer, Jiri. Regarding the clock distribution in the case I would use 2 DDR chips, is it dangerous to have a star-topology (that is, ONE...
hi all, I have a question about interruption handling in Leon3. The documentation says that the interruption are automatically acknowledge by the processor,...
... GrmonRCP Update: An update to GrmonRCP is available from Software Update (Help -> Software Updates...) This updates GrmonRCP to use GRMON 1.1.22 and also ...
Dear Jiri, I'm evaluating the capabilities of the TSIM simulator and its module interface at the moment. When writing TSIM modules, is it possible to access...
hwulf@...
Sep 6, 2007 5:35 pm
11851
A loadable module can of course access any function or service from the operating system. You can thus open files, sockets or any other devices. Jiri....
hi all, I have a question about how does the LEON3 communicate with the SmSc Ethernet controller on altera Stratix II card . otherwise, is the SmSc connected...
* The SMSC LAN91C111 10/100 Ethernet controller is attached to the I/O area of the memory controller at AHB address 0x20000300. The ethernet interrupt is...
Hi, all There are many warnings reporting some output ports, such as fpi.d.pc, cpi.lddata, have no drivers in iu3 module. I wonder if it matters. Thank you!...
Hello, I read some topics in the forum and I noticed to some people have the same doubt mine. I want compile and simule a program (C) on RAM memory, using...
Hi Jiri, I can read from gaisler.com that the core of Leon3 "will reach up 125 MHz on FPGA". Am I right to conclude that using DDR-Sdram with FPGA is totally ...
Let's consider a design inside an FPGA running @125 MHz max (for instance Leon3/Grlib), interfacing with a DDR Sdram chip @133 MHz. To really take benefit of...
You can use a 16-bit DDR memory, and still have the same bandwidth as a 32-bit SDR. Or you could add a second AHB port the the DDR controller and use it for a...
... We might add an extra pipe stage for the data cache access, to avoid having to do cache tag access and tag compare in one clock cycle. This feature is...
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