See the GRLib IP core manual (GRIP.pdf), see APBUART Control Register look for "Receiver Enable". It is the same register which had the value 0xa2. Use wmem in...
Probably a synplify error - upgrade to 8.8 or later. Alternatively, do not install the the VHDL FPU netlists for stratixii (in lib\techmap\stratixii). Jiri....
Since the gated clock and the free-running clocks must be phase-aligned, clock gating will only work on technologies with zero-delay clock multiplexers or...
On the first problem I want to say, where is the time of the simulation(ps). when the simulation ends. What's the file who contains the time Time: 299611998 ps...
Hello, I am debugging a Leon3 (2 CPU's) application on eCos & GRSIM inside Eclipse, and I found that an access to a valid memory position is reporting a SEGV. ...
Not in detail. The grlib manual (grlib.pdf) explains how the plug&play signals work in leon3. What you need to do is to add these to your AHB/APB cores and...
As I said several days ago, I think the templetes in grlib release version must be ok but failed. I think it result is helpfull for someone and thanks for any...
Hello people, I want to know if its possible to produce stall on Leon using ld instruction.. i.e: If my program repeat this line ever and ever (10000 times) ...
Yes, the first time will make a cache miss and the other 9999 times will not. The first "ld [%fp-12], %g1" instruction will make a cache miss but the second...
... Hash: SHA1 Hi Jiri, I have checked with Eclipse 3.2.1, CDT 3.1.2, plugin 1.2.2, and same behaviour. But I found the cause of the error: I have the...
You ALIGN statement does not look correct, the sections should be aligned on at least 8, or better 16 ... Are you sure you are using the original linkfile as...
Hi All, Does anyone know of any method for speeding up RTL simulation with an FPGA? I've some small changes to the Leon3 iu module and want to speed up...
Hi Jiri, I tried to design an AHB slave module which uses the hardware timer to record the timing for program execution. I create my design follow the "ahbram"...
Hi all: Who has compiled grlinux for nuhorizons-3s1500 development board? My OS is Centos and I try to run linux on my system as follow steps: 1- / > tar -jxf...
Hello I was wondering if there is a way to make tsim report the instruction count at the end of the simulation. Something like: add 1500 cmp 350 sub 25 ......
Hello, I would like to know how I can modify the speed and synfreq(they are located on the board folders), using the QuartusII GUI. For example, the folder...
Hello, Is there any site that contains small benchamarcks to simulate them with ModelSim? The dhrystone simulation is so slow, I want smaller benchmarcks. -- ...
Your design is using too many clocks, that is why the Quartus fitter cannot place it. This is fairly obvious if you would read the error messages in the log. A...
hy people I have synthesised all the Leon3 Rpocessor Core usaing the RTL compiler and the Synopsys Design Compiler. And I am trying to make the pos-logic ...
Hello everyone - I have a question about the Leon cache. As specified in the documentation, the L1 cache fetches only the requested word on a miss (rather than...
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