Hello. I'm looking for doing a new amba Ip Block. I've read all the amba chapter in the grlib manual but i still don't understand how to calculate the mask. ...
... Depending on the type of memory area (i.e. AHB I/O, AHB memory bank) a slice (or range) of the incoming address is compared with the address in the bar....
Hello all I am trying to figure out the amount of instruction and data cache misses in the Leon3 from RTL simulation. Does anyone know which signal/s I should...
Thanks for the information, I have got a better view now. What is the absolute differences between both types ? because both of the memory or the I/O are r/w...
Hello, I am trying to run snapgear in a LEON3 system mounted in the altera-ep2s60-sdr template design. I configure the bootloader for the flash memory in the...
The SDRAM banks number should be 1, not 4. The value indicates number of chip selected banks, not the number of internal banks in the SDRAM devices. Also,...
I suggest you do the following: 1. Download a fresh grlib-1.0.18 package from: http://www.gaisler.com/products/grlib/grlib-gpl-1.0.18-b2950.tar.gz 2. Unpack it...
Hi all, It may be not an appropriate question here. But I would greatly appreciate it if someone can help me. AMBA specification requires slave to respond...
hello...can i run a program from the AHBRAM and view the simulation results on quartus II? currently, i'm running from local instruction ram through a mif...
Hi... I'm trying to run programs compiled by GCC on a LEON3 core. I'm able to run programs that include addition and subtract instructions (make sure you...
Hi all, I try to test the correctness of a AHB/PLB bus bridge, but there are simpl too many possible situations to cover. I think I may have only covered 25%...
... starts write ... few clock ... (potentially) ... on the ... I assume it is write an allocate cache. It writes through the cache but allocates a line in the...
Under certain conditions I'm trying to perform a cold-boot of my software, by restarting from PROM address=0. The following sample program run from FLASH. It...
The psr.tt field is not cleared when you do a soft-reset by jumping to 0x0, so the software will think is is a normal trap. You will need to jump to...
I just wanted to follow up with this post. I eventually manged to get the design synthesizing and working without too much difficulty. However, I still found...
I am getting the same error, IU in error mode (tt = 0x80) 4000d980 91d02000 ta 0x0 as soon as I run a program. I tried single stepping it, but it steps ...
... I'm not sure, do you mean the PSR.ET field or TBR.TT ? According to the SPARC V8 architecture the (p.75) the TBR.TT is undefined at power-up, so I guess...
The psr.tt is reset when SVT is enabled in the processor config: if (xc_rstn = '0') then . if svt = 1 then v.w.s.tt := (others => '0'); end if; . So after...
... See the "LEON3 quick-start guide" in the GRLIB IP Library User's Manual ( http://www.gaisler.com/products/grlib/grlib.pdf ). The most convenient way is to...
Hello I'm using grmon-eval with a M7A3PE600 Target. When I execut it, it prints 'try open device //./Com1' and nothing. So is it a com port problem or anything...
Problem solved. Turns out, it was another ROM related hardware problem (the previous problem was that debugging requires a ROM to work). The processor doesn't...
I forgot to mention that I was using the default config.vhd file which has ROM pipelined access on which, as stated, doesn't work when ROM is implemented in...
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