hi, all One quick question, if i want to store my data into the SDRAM, and load my application to execute this data. Which address is good for it? Because i am...
Grmon supports loading of binary files to an arbitrary address, see the manual for the 'bload' command. If you lower the stack below the top-of-ram (use the...
Hello, ... I installed the netlist-package. but the problem isn't solved. I get the same error message. Thirst I thought that there is a problem with the ...
... "tech" here can be spartan3, virtex4, etc. ... If you want to use the Xilinx netlists you should NOT say yes to the "Use netlist" option in xconfig. If you...
A new release of GRTools is available from http://www.gaisler.com/cms/index.php?option=com_content&task=view&id=272&Itemid=31 GRTools is our all-in-one...
Have you turned off Accelerated UART tracing under VHDL Debugging when running make xconfig. /Magnus...
Magnus Sjalander
magnus@...
Oct 3, 2008 7:40 am
13933
Hello, thirst thanks for helping with my other problems. Now I synthesized Leon3 with FPU and there is no error anymore. Now I have problems after flashing the...
... It is possible. However then the tools should tell you so. Did your design fit in the device? Did you meet the timing requirements? If you instantiate...
... the tools did not say anything about the space.. And when I flash the board with iMPACT there is now error or something else.. It looks good.. ... left ......
... OK, so the utilization summary in the log file leon3mp.par looks ok? (Just to be sure) ... If all timing checks were OK there may be some other problem.. ...
... OK, I never read the par file.. and of the end of the synthesizing was no error, so I thought that everything is okay.. How can I optimize it.. Thanks for...
... The simplest solution is to drop the SVGACTRL or GRETH core. But you probably need those? Otherwise you can try: - Playing with the tool switches to...
Is there a way to force IU to store result in regfile and then read it back, rather than use the result from the pipeline register, even if instructions using...
Hi, when I try to generate a Post-Place&Route Simulation Model, I have an error. I'm using Xilinx ISE: ERROR:ProjectMgmt - TOE: ITclInterp::ExecuteCmd gave Tcl...
Hi everyone, I have synthesized a typical Leon3 processor with grlib-gpl-1.0.18-b2950. I used the preset design "leon3-xilinx-ml505", but the board i am using...
Do a 'flash status' to check that all blocks are unlocked before programming. If not, power cycle the board, do a 'flash unlock all' and check the status...
Ignore the previous reply. Your problem is that you are trying to program a RAM image into PROM. This will obviously not work. grlib> flash load hello.exe ...
Hi, with the command make ise I synthesize and place&route the file leon3mp.vhd, but I want to the same to the testbench instead of leon3mp.vhd which changes...
Hi Jiri, I only want to synthesize and place&route the testbench for simulate it, not to implement it in a FPGA. When I try to do that with Xilinx I have a lot...
Hi Jiri: When I use t1-xilinx-ml507 template. I simulate it and found the error like "tbench.ddr2mem__3.u1.cmd_task: at time 9506678.0 ps INFO: Initialization...
The ML507 board can not be simulated since the DDR2 memory models do not support pre-loading of data. I would suggest that you simulate the t1-gr-cpci-xc4v or...
Read my reply again - you cannot synthesize the test bench since it contains non-synthesizable behavioral models of various memories. You should simulate the...
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