I have successfully configure 16-bit flash memory of my board. Now I'm trying to use 8-bit flash memory. The Intel 28F320J3 Flash memory has 'nByte' signal,...
Sanghyun Park
shpark@...
Jan 2, 2009 8:40 am
14505
Hi Mohammad, ... This should be assembler-with-cpp (without space)... So check your makefile. Regards, -- Jonas Flodén Gaisler Research AB jonas@... ...
Dear All, I have a Xilinx Virtex5 board which has a 16-bit SDRAM on it. I want to port Leon3 on it. Does the memory controller of Leon3 support 16-bit SDRAM? ...
Thank you very much. But in this link, http://www.gaisler.com/cms/index.php?option=com_content&task=view&id=12&Itemid=52 *Links to other LEON sites and...
Hi all, I have some trouble to get the JTAG parallel cable IV operational. Therefore, the questions below might lead to an answer. Question 1: Can an LPT port...
In GRLIB, 16-bit SDR SDRAM is not supported. That's not official project, and appears to no longer valid. You can look for other refernce, implement and add...
Hi, I need help about tsim and simulation of a coprocessor user defined. In tsim's manual it's specified how load a coprocessor module, but I don't understand...
It should be in the directory that you start the simulator. if in doubt, use the -fpm or -cpm switch define the file location. Note that you need the...
Hi, I tried to create a program witch should be placed in sram.srec and invoked by the prom.S program but when I compile it using the BCC for Linux, I obtain: ...
Hi, I have a problem with forwarding application console I/O. On page 21 the GRMON user's manual states: <quote> With FIFO debug mode it will also be possible...
Dear Jiri, Thank you for the quick response, but unfortunately even after following your suggestions the problem still exists. As stated in the original post,...
Hard to say what your problem is. We can boot linux over grmon using the -u, so the interrupts work or linux would not see any console input. Which version of...
Dear Jiri, Thank you again for your fast response. I'm using: GRMON LEON debug monitor v1.1.32 (evaluation version) as debug monitor and a standard bitstream...
Hi Jiri: U said that in XUP design readme.txt "* The JTAG DSU interface is enabled and works well with GRMON and Xilinx parallel cabel III or IV . The on-board...
Hi, External SRAM can have two banks through proper RTL setting. However how can program access two banks? I think we should have proper memory map to select...
Great Jiri: May u help me to let me know what the issue is. Why on board usb jtag is slower than parallel jtag? Because I dont want buy another parallel IV...
The USB interface from grmon to a Xilinx cabel/board is slow since the cable API is not made public by Xilinx, and we have been forced to reverse engineer it....
Hi Jiri: Thanks for u reply! You always be kind to resolve us issue. Maybe I can use ahb uart not jtag port to debug the CPU? will it be faster than usb jtag? ...
... All processor will execute same program for SMP system, but we can make branch by processor id, and make them execute different code. cpu 0 cpu 1 ......
Hello, I manage the leon configuration and manuals but I cannot find how to configurate the leon (without MMU) in order to obtain that rom code and a part of...
Hi, Has anyone tried using grmon through bluetooth spp (serial port profile)? This includes reading out values as well as uploading programs such as...
Hi, thanks for the answer. The problem is that I don't need to enable or disable the MMU. I must disable it and activate a partitioning on memory static...
The cachebility can be set through the CACHED generic as explained in the grip.pdf manual, section 52.2.16. The generic can be set in the xconfig menu under...
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