hello,all now i build a testbench for my design,when i want to do a base_test ~{#,~}i only use prom.h,prom.s,systest.c under designs/leon3mp to copy under my...
... With GRMON over a debug link I would say that it matches the programming speeds I have seen. ... There could definitely be changes made in how GRMON...
Hi Jan, If u think it is normal I would ignore it. Thouhgh I wanted to use a higher speed and tried to find something about (xup x2p) program spi flash...
i have compiled a design of modelsim and i have a problem with run all. when i make this command in modelsim windows i have this message: hi rihab i the...
hello when i make this command in model sim i have this message # ** Fatal: (vsim-7) Failed to open VHDL file "disk.srec" in rb mode. # No such file or...
The fifo size or burst length for the DD2 controller can not easily be changed. To do this, you have to rewrite large parts of the controller. /Nils...
... Impossible to say without knowing which template design you started from, what modifications you made e.t.c.. Note that you must perform a 'make soft' to...
... You are setting the stack pointer to where your code is. Try setting it higher up in the ram. <snip> ... Also enable accelerated UART tracing (CFG_DUART in...
... The default behavior of 'make soft' is to compile systest.c and copy the executable code to .srec files which are loaded by the memory models that are used...
... Impossible to say without know which template design you started from, what modifications you made e.t.c.. Note that you must perform a 'make soft' to...
... You should start modelsim with 'vsim testbench' or double click on the testbench entity in modelsim to load it before doing 'run -all'. Best regards, Jan...
... You could try to create an empty disk.srec, or copy sram.srec to disk.srec, or remove the instantiation of ata_device from testbench.vhd. Best regards, Jan...
i do it on altera-ep2c35f�and i did recomplie the systest.c. i look at the wave of modelsim ,and find out that the debug.error is "U"��thank you for...
... Did that design already have prom.h, prom.s, and systest.c? All these files may may contain specific code for a template design so it is not always...
hello in cygwin i make this command make quartus .this command permit the synthesize and place&route . So i obtained succes but i don't find the binary file in...
... The resulting bitfile should be called $(TOP).sof. The value of TOP is defined in the design's Makefile. For leon3-ge-hpe-mini it is leon3mini. Best...
thank you very much ,i did copy the prom.h, prom.s, and systest.c file from the designs/leon3mp,i think the files prom.s, and systest.c are in directory...
... yes ... It runs applications from the Quartus suite. If you look in <grlib>/bin/Makefile you will see the quartus-target (quartus:). See the Quartus II...
i think you overlook the board info i use,hehe, my design is on altera-ep2c35f not altera-ep3c35f, the hconfig/pconfig info of the base_test modules in...
helo i want to understand the differnet function of systest but i'm not good enough in c . can i find a file that contain an explication or is there anyone who...
... Then I assume that you are running an old version of GRLIB since there is no leon3-altera-ep2c35f design in version 1.0.20. That is why I suggested that...
Hello, I use the GRPCI IP in my Leon3 design. Initially, we wanted to use the interrupts of the PCI bus. But after studying the specifications and the PCI bus...
Hi, I’m trying to run snapgear linux 2.6.x on flash prom using grmon through eth. ===================================================== ./grmon-eval -eth -ip...
윤종희(W)
jhyoon@...
Apr 2, 2009 7:35 am
15163
Hi, I’m trying to run snapgear linux 2.6.x on flash prom using grmon through eth. ===================================================== ./grmon-eval -eth -ip...
윤종희(W)
jhyoon@...
Apr 2, 2009 7:36 am
15164
... Thank you fou your reply,CFG_DUART in config.vhd i have set it to '1',and the stack pointer is also changed. My operates in the following steps: (1)$...
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