Hi, I want to interface a custom FPU to LEON-3, the FPU has following interfaces: entity myfpu is Port ( clk : in STD_LOGIC; reset_n : in STD_LOGIC; opcode :...
... I believe that you should probably not iterate at all then? ... From a quick look, just iterate from 0 to 0. ... Edit leon3mp.vhd and do not instantiate...
Hi, Modelsim is 6.4 and of course, I didn't touch HY model file. Can you provide me correct value of rdata(0)? Or data values in hexread() when reading...
Dear all, We are trying to develop own diagnose software to work with Leon3. We opt to use the GRETH debug interface. However, there is an interesting issue...
... Not without knowing the 'index' and the address that is currently being read. If you are loading the sdram.srec that comes with the ml510 template design...
In the grip manual the ctrl word is shown with the msb to the left. The Edcl expects that the msb is received first and the lsb last. The same applies for the...
Do you run the different operating systems on the same computer and with the same network equipment (switches etc)? If you have selected a strange MAC address...
Hello, I am trying to place a small C program (just prints ''hello world'') into an AHBROM. I followed the mkprom2 build-flow and I am able to create an...
Bernhard Froemel
froemel@...
May 4, 2009 9:55 pm
15539
It seems that Synplify is not creating correct memory initialization ... . . ... -- Bernhard Froemel Tel: +43 2279 26 222 0 Institute...
Bernhard Froemel
froemel@...
May 5, 2009 8:03 am
15540
This seems to be a synplify bug - you should report it to Synplicity. Try to switch back to synplify-9.6.2, which seems more stable to me ... Jiri....
Hello, My aim is to evaluate the leon3 processor on the Altera Cyclone II FPGA and more precisely on a Microtronix board with a Firefly II module. So I am...
I have actually tried on Windows, a VMWare with Fedora on the same machine, and other separate Linux and Windows machines. But, yes, maybe you're right. I'll...
Hi, we're 2 students doing a project using the LEON3. We would like to demonstrate our project using the VGA and PS2 on our Virtex4 development board. We...
The Bare-C runtime does not have a VGA or PS2 driver, all stdio is sent via the UART. So you must either develop your own drivers or use an O/S with VGA/PS2...
In fact I have found all the needed information in the documentation writen by 'Lutz.Buttelman' : 'How to setup VHDL simulation with ModelSim'. So thanks for...
Hi all, I am trying to load an EXE file to main memory. Basically, I compile the assembly language and generate .exe file (binary code). What I want to do is...
Hi, I¡¯m using the latest grlib, and connected SDRAMs to MCTRL. My sdrams are working in 32bit mode, and using the sdclk which is generated from virtex5 DCM....
Sanghyun Park
shpark@...
May 6, 2009 4:11 pm
15549
Hi, I am compiling an application using bcc as follows- sparc-elf-g++ -o test main.cpp I want to change the register window size, so I am running TSIM with the...
Hi Eisele, Thank you for your suggestion. I think I didn't express my question very clearly. Actually, I know I can load the exe file by using "load" command...
... You have to search for the elf file format specification. You could for example use binutils bdf library, which exports elf handling routines. -- Konrad...
Hi, Is there any template design of leon3mp in GRLIB that can be synthesized, place and routed using both Altera Quartus and Xilinx ISE? Since template design...
Hi Eisele, Thank you so much for your great help! Yesterday I found the ELF specification and wrote a simple code. I will take a look at the routine you...
hello, all i use the grlib grlib-gpl-1.0.12-b1888. now i debug the SVGACTRL on the board on which the FPGA is ep2c35f672c8, and the lcd is sharp 18-bit tft-lcd...
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