Hello all, I am trying to use the GENIO pins on the gr-xc3s1500 board along with the leon3 processor to interface external peripherals. I looked at the archive...
I assume those pins are directly connected to the FPGA, so it very much depends on what periphery you want to interface. If its just general purpose I/O to...
Bernhard Froemel
froemel@...
Jun 2, 2009 6:14 am
15675
... The standard Leon3 template for the gr-xc3s-1500 board which Aeroflex Gaisler provides as part for the grlib-gpl distribution, includes the grgpio I/O port...
I'm trying to expand the testbench to have complete code coverage. I've made great progress and have > 80% coverage, but half of the remaining missed code is...
Hi I use eCos with leon 3 and i would like to set an array address at a sram. I try 2 things: 1) #pragma DATA_SEG PORTA_SEG volatile unsigned int array[32767];...
Hi, we get a problem when we do 'make' in both snapgear-2.6-p37 and snapgear-2.6-p39. Note that we have already done 'make xconfig'. This is the printout we...
... The manual for the LCD controller should list the required timings. When you have the values for active video, front porch, back porch and sync length you...
... You are not providing enough information about your AES core.. If it is not AMBA compliant you will need to develop a wrapper with an AMBA AHB or APB slave...
... Please see section 3.4 in the GRMON manual for information on how to set break points and using a trace buffer (you will need to configure the hardware to...
Thanks you for your answer but with this solution the memory area is not protected to the overlapping and my problem is eCos writes in this area. if an array...
I'm working with leon on a xilinx ml505 board. I already did the synthesis with 'make synplify' but I'm getting an error when I try place&route with 'make...
... What do you mean with overlapping? I thought that you want to access a fixed address somewhere in the address space. If you need just memory then try...
Hi, I am using the leon3mp design on modelsim. The programs I am trying to run are relatively big and when I simulate the design I keep getting an error while...
I would like to have 4 arrays: short a[19200] short b[19200] short c[19200] short d[19200] And I would like to force theirs addresses to a= 0x400B0000 b=...
Hi Rawan, I think this depends on the size of mt48lc16m16a2 sdram (u can check the size of its array of cells), u can use other sdram of a configurable size or...
Hi Jiri, Jan, LEON3'ers, I have some queries with the testbench for the GR-XC3S-1500 board that I can't seem to get working correctly. My core is an ahb...
Price inquiries should be mailed to sales@.... Our sales department follow their own (fuzzy) logic when it comes to publicizing the price list ... :-) ...
Hi all, When i simulate grlib-gpl-1.0.20-b3403/designs/leon3-actel-proasic use the command:make xgrlib .I have do no changes to the template,and then use...
Hi all, Is there anybody who uses Actel FPGA and the design template: leon3-actel-proasic3? NOW ,I only have a Actel FPGA Fusion development Board.I want to...
Hello, I am interested in synthesizing Leon3 using Design Compiler, but the compile.dc script does not seem to make optimizations for memory structures. Is...
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