Hi, I'm currently working with interrupts and I'm facing a strange error. I took the file c-irq.c and it's working fine on my design. However I tried to read...
Hi, I'm experiencing problems simulating software with modelsim. I start with a simple "hello word" program : #include <stdio.h> int main(int argc, const char*...
Dear all, We constantly get problems with GDB source level debugging of a mkprom2-generated Leon3 binary (execute-in-rom configuration): sparc-elf-gdb reports...
actually the path is set as this /cygdrive/c/ but in error message it gives this type of error "could not find c:program" . But I have resolve this problem as...
Another question, maybe easier, but that would also solve my problem : Instead of making a boot-prom, I first tried to keep the original boot-prom prog, and to...
... The design was not updated when pci_rst in pcipads was changed from in to inout. The fix should simply be to change the direction of pci_rst in ... +++...
... Just make sure to assign a unique APB/AHB indexes and addresses and you should be fine. You can add new configuration parameters directly to config.vhd....
Hi, The reason for the current implementation is that the clock resources are limited and the use of to many BUFG cells creates a design that can not be...
Magnus Sjalander
magnus@...
Jul 1, 2009 1:54 pm
15784
Hello, ... The DDR memory contents is loaded from sdram.srec. I tried with the unmodifed leon3-xilinx-ml506 design here and it executes the application in...
Hi, My name is Eugen Leontie, a doctoral student in the Computer Science Department at George Washington University in Washington, DC. My group is looking at a...
Hi, I'm using the latest version of bcc compiler with leon3. I can't get printf working with long long (%lld). Is this a newlib limitation, i.e. are others...
... Hi, newlibc is compiled without vfprintf support for ("ll"). You need to recompile newlibc using "--enable-newlib-io-long-long". (the newlibc sources are...
Thank you for your help. Well, I've alreay tried to use sdram.srec instad of sram.srec, but it doesn't change anything. As I saw, in testbench.vhd, constant...
I don't think using directly the DCM is better for the timing. But actually ISE don't see clk180r and clk270r as clock (clock Region report). So it is not...
... What error was that? ... Yes, pre-loading was added in 1.0.20. ... There has been a post about that error earlier on the list. The best guess at that time...
I understand. I've tried 2 versions of ModelSim, and the problem exists with both : 6.4a (old) 6.5b (latest) Thank you for your help, I'll search the list for...
Hi, I would like to know which busts are implemented in the LEON3. When I simulate it on modelsim, it seem to use only "single transfer" (no burst) and...
Hi, It is difficult to judge which of the implementations that would achieve the best results. Why not try to make the modification and see if you manage to...
Magnus Sjalander
magnus@...
Jul 2, 2009 11:24 am
15798
Thanks for getting back to me Jiri and excuse me for the late reply. In the meantime, I was able to get the 16-Bit PROM access working. Your suggestion to...
... From the data I have been able to gather: 6.1e: Working 6.2f: Working 6.3f: Working 6.4a: Fails 6.5a: Fails I do not see anything wrong with the code. The...
Thank you very much for you helpful work ! It does work now, and I get the following : # Xilinx ML506 Development board # GRLIB Version 1.0.20, build 3403 #...
hello jiri, i have written a test application( SYSTEST ) in assembly language(using sparc instruction) instead of writting in 'c' language. so which command i...
Hello all, I am trying to control an external peripheral IC using the memory expansion connector on the gr-xc3s1500 board. The peripheral IC is controlled...
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