hello Sir, I want to verify leon3 based SoC. i.e functional verification,code coverage analysis.there is no any example in verification of grlib.I have...
Hi Jan, Thanks for your reply :) By saying "performing AMBA read and write" you mean SPARC load and store instructions?? or is there another way? Regards, ...
The manual describes what the DDR controller core does for you ("An AHB read access to the controller will cause a corresponding access to the external DDR...
Hi, just for your convenience: the default linker script can be retrieved by sparc-elf-ld -vebose You can than modify and add segments by hand. Cheers, Philip ...
You need to create a custom link script for gcc that defines RAM in your area. See the gcc docs for details. The default BCC link scripts has RAM in 0x40000000...
Hi all, While i was reading in grip manual, DDR2SPA section, in the "Read cycles", it tell that if i want to read i have to perform ACTIVATE command and then...
Hello, Jiri. I'm using BCC for Leon3. The memory that will run the app is at 0x10000000 but i can't compile with that address as text area. Can you give me any...
Hi Jiri, also, I tried to run it directly under the path of `../grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800', using original files from the unzip...
Hi Jiri, 1. I am using bshell, all the environment variables are set in the .bash_profile file 2. after make script, it is the makeFile in the design...
This is not what I asked. Again: 1. Which shell are you using? 2. If you do an 'ls' in the design directory, which files do you see after doing 'make scripts'...
Hi Jiri, I have some probem when running make vsim. it reports as below. I checked my GNU VERSION by 'make -v', as below. My grlib is unziped by 'gunzip -c...
This is not possible. Use coregen if you need this feature or write such a module yourself. It is not too difficult, the pre-initialized data is defined on the...
Hi Jiri, I wonder if i can initialise a ahbdpram by using a init data file? as what we do in Xillinx coregen. I tried to modify the library, but it does not...
Hi Jiti, Please skip the previous question. I just saw it is actually two two-port rams with the combination of the write bus. there is no ahb interfaces for...
Hi Jiri, i want to add 'regfile' ipcore in grlib to my design. The doc says it is actually a three-port ram. the device i am using is xilinx sp3a-dsp-1800a. i...
Hi all, I hope you can help me. We are currently developing a system on an Atmel AT697E processor and have a requirement to be able to trap a data access...
Now I have run the synthesis with XST as well and can verify that it is a XST problem. None of the debug links can access the design when fixed priority is...
Why can't I creat an application with the instruction area (-Ttext) between 0x1000000 and 0x3fffffff? The Leon i used has a flash memory on 0x10000000 bus and...
I have followed the same procedure you used and it worked straight off with both ise 9.2 and 10.1 regardless of the arbitration setting. Are you using XST for...
Hello, Could you tell me if I need add a new technology to the library for the Xilinx SP3a-dsp FPGA, or I can just use spartan3 in my technology setting?...
... In simulation it is probably easier to capture the complete output and then search for the address of the store that you suspect of doing something wrong....
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