Hi again,

have you tried make vsim-launch?It will open the gui but i dont have the problem
tha has the script and i can sim my design without problems...

John

--- In leon_sparc@yahoogroups.com, "jarvanitakis" <jarvanitakis@...> wrote:
>
> Hi,
>
> i have the same problem when i try to make vsim...I also noticed that the
"manual" from Lutz Buttelmann thats uploaded on the group has the same error on
the report...
>
> Is there anyway that we can fix it?
>
> thanks,
> John
>
> --- In leon_sparc@yahoogroups.com, 张�&#65533;维 <yiwei.zhang@> wrote:
> >
> >
> > Hi Jiri,
> >
> >
> >
> > also, I tried to run it directly under the path of
`../grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800', using original
files from the unzip pack. in this case, make script works well ,report:
> >
> >
> > [eexyz@een5021 leon3-xilinx-xc3sd-1800]$ make scripts
> > Scanning libraries
> >   grlib: stdlib util sparc modgen amba
> >   unisim: ise
> >   dw02: comp
> >   synplify: sim
> >   techmap: gencomp inferred dw02 unisim maps
> >   eth: comp core wrapper
> >   gaisler: arith memctrl leon3 misc net uart sim jtag greth ddr
> >   esa: memoryctrl
> >   fmf: utilities flash fifo
> >   spansion: flash
> >   gsi: ssram
> >   cypress: ssram
> >   hynix: ddr2
> >   micron: sdram ddr
> >   work: debug
> >
> > leon3mp_synplify.prj
> > leon3mp_dc.tcl
> > leon3mp.rc
> > leon3mp.xst
> >
> >
> > ---------------
> >
> >
> >
> > but after that, when i run 'make vsim', it reports:
> >
> >
> >
> > [eexyz@een5021 leon3-xilinx-xc3sd-1800]$ make vsim
> > Reading /app/modelsim64/modeltech/tcl/vsim/pref.tcl
> >
> > # 6.4a
> >
> > # do libs.do
> > #  quit
> > make[1]: Entering directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
> > make[1]: make.vsim: No such file or directory
> > make[1]: *** No rule to make target `make.vsim'.  Stop.
> > make[1]: Leaving directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
> > make: *** [make.work] Error 2
> >
> >
> > ----------
> >
> > but i can see the compile.vsim file has been generated. very strange. Then i
had another go to start modelsim, and run 'do compile.vsim', it reports:
> >
> >
> >
> > [modelsim]>> make vsim
> > # make[1]: Entering directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
> > # make[1]: Leaving directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
> > # make[1]: make.vsim: No such file or directory
> > # make[1]: *** No rule to make target `make.vsim'.  Stop.
> > # make: *** [make.work] Error 2
> >
> >
> > [modelsim]>> do compile.vsim
> > # ** Error: Library std not found.
> > # ** Error: VHDL Compiler exiting
> > # ** Error: /app/modelsim64/modeltech/linux_x86_64/vcom failed.
> > # Error in macro ./compile.vsim line 1
> > # /app/modelsim64/modeltech/linux_x86_64/vcom failed.
> > #     while executing
> > # "vcom -quiet  -93 -work  grlib ../../lib/grlib/stdlib/version.vhd"
> >
> >
> >
> >
> >
> >
> >
> > i can see the library list is generated in modelsim but all are empty, since
vcom is not executed correctly. any suggestion? thanks!
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> > To: leon_sparc@yahoogroups.com
> > From: yiwei.zhang@
> > Date: Fri, 13 Nov 2009 18:31:26 +0000
> > Subject: RE: [leon_sparc] make vsim
> >
> >
> >
> >
> >
> >
> > Hi Jiri,
> >
> >
> >
> > 1. I am using bshell, all the environment variables are set in the
.bash_profile file
> >
> >
> >
> > 2. after make script, it is the makeFile in the design directory:
/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800
> >
> >
> >
> > because there is no Makefile in the path:
/grlib-gpl-1.0.21-b3848/boards/xilinx-spa3-dsp1800a, I copy the one in the
'designs' path to the 'boards' path, and point this directory in the 'Make
scripts' script. Any problem to do that? thanks.
> >
> >
> >
> > vv
> >
> >
> >
> >
> >
> >
> > To: leon_sparc@yahoogroups.com
> > From: jiri@
> > Date: Fri, 13 Nov 2009 17:53:10 +0100
> > Subject: Re: [leon_sparc] make vsim
> >
> >
> >
> >
> >
> >
> > This is not what I asked. Again:
> >
> > 1. Which shell are you using?
> >
> > 2. If you do an 'ls' in the design directory, which files do you see after
> > doing 'make scripts' ?
> >
> > Jiri.
> >
> > 张�&#65533;维 wrote:
> > > Hi Jiri
> > >
> > >
> > >
> > > I am using Linux. the makefile is the one. I modified the GRLIB to the
directory where the grlib locates. Thanks.
> > >
> > >
> > >
> > > include .config
> > > GRLIB=../../grlib-gpl-1.0.21-b3848
> > > TOP=leon3mp
> > > BOARD=xilinx-spa3-dsp1800a
> > > include Makefile.inc
> > > DEVICE=$(PART)-$(PACKAGE)$(SPEED)
> > > UCF=$(TOP).ucf
> > > ISEMAPOPT=-timing
> > > QSF=$(TOP).qsf
> > > EFFORT=high
> > > XSTOPT=-uc leon3mp.xcf
> > > SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option
-write_apr_constraint 0"
> > > VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
> > > VHDLSIMFILES=testbench.vhd
> > > SIMTOP=testbench
> > > SDCFILE=default.sdc
> > > BITGEN=default.ut
> > > CLEAN=soft-clean
> > >
> > > TECHLIBS = unisim
> > >
> > > LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
> > > tmtc openchip ihp gleichmann opencores usbhc spw
> > > DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest can
\
> > > usb grusbhc spacewire ata haps coremp7 ascs slink spi hcan
> > > FILESKIP = grcan.vhd i2cmst.vhd
> > >
> > > include $(GRLIB)/bin/Makefile
> > > include $(GRLIB)/software/leon3/Makefile
> > >
> > >
> > >
> > >
> > > To: leon_sparc@yahoogroups.com
> > > From: jiri@
> > > Date: Fri, 13 Nov 2009 16:53:12 +0100
> > > Subject: Re: [leon_sparc] make vsim
> > >
> > >
> > >
> > >
> > >
> > >
> > > Which host OS and shell are you using? If you do an 'ls'
> > > in the design directory, which files do you see after
> > > doing 'make scripts' ?
> > >
> > > Jiri.
> > >
> > > vvzmvv wrote:
> > >> Hi Jiri,
> > >>
> > >> I have some probem when running make vsim.
> > >> it reports as below. I checked my GNU VERSION by 'make -v', as below.
> > >> My grlib is unziped by 'gunzip -c grlib-gpl-1.0.21-b3848.tar.tar | tar xf
-. So i have no idea where is wrong. My modelsim is modelsim SE 6.4. So could
you give me any suggestion? Many thanks!
> > >>
> > >>
> > >> [eexyz@een5021 ~]$ make -v
> > >> GNU Make 3.80
> > >> Copyright (C) 2002 Free Software Foundation, Inc.
> > >> This is free software; see the source for copying conditions.
> > >> There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A
> > >> PARTICULAR PURPOSE.
> > >>
> > >>
> > >> ---------------------------------------------
> > >>
> > >> [eexyz@een5021 leon3-xilinx-xc3sd-1800]$ make scripts
> > >> Scanning libraries
> > >> grlib: stdlib util sparc modgen amba
> > >> unisim: ise
> > >> dw02: comp
> > >> synplify: sim
> > >> techmap: gencomp inferred dw02 unisim maps
> > >> eth: comp core wrapper
> > >> gaisler: arith memctrl leon3 misc net uart sim jtag greth ddr
> > >> esa: memoryctrl
> > >> fmf: utilities flash fifo
> > >> spansion: flash
> > >> gsi: ssram
> > >> cypress: ssram
> > >> hynix: ddr2
> > >> micron: sdram ddr
> > >> work: debug
> > >>
> > >> leon3mp_synplify.prj
> > >> leon3mp_dc.tcl
> > >> leon3mp.rc
> > >> leon3mp.xst
> > >> [eexyz@een5021 leon3-xilinx-xc3sd-1800]$ make vsim
> > >> Reading /app/modelsim64/modeltech/tcl/vsim/pref.tcl
> > >>
> > >> # 6.4a
> > >>
> > >> # do libs.do
> > >> # quit
> > >> make[1]: Entering directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
> > >> make[1]: make.vsim: No such file or directory
> > >> make[1]: *** No rule to make target `make.vsim'. Stop.
> > >> make[1]: Leaving directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
> > >> make: *** [make.work] Error 2
> > >>
> > >> ----------------------------------
> > >>
> > >> thanks!
> > >>
> > >> vv
> > >>
> > >>
> > >>
> > >> ------------------------------------
> > >>
> > >> Yahoo! Groups Links
> > >>
> > >>
> > >>
> > >>
> > >
> > >
> > >
> > >
> > > __________________________________________________________
> > >
MSN�&#65533;&#65533;�&#65533;�年�&#65533;�&#65533;��&#65533;�&#65533;��&#6553\
3;&#65533;MSN注�&#65533;&#65533;�&#65533;��&#65533;��&#65533;赢�&#65533;&#655\
33;�&#65533;�&#65533;大�&#65533;
> > > http://10.msn.com.cn
> > >
> > > [Non-text portions of this message have been removed]
> > >
> > >
> > >
> > > ------------------------------------
> > >
> > > Yahoo! Groups Links
> > >
> > >
> > >
> > >
> > >
> >
> >
> >
> >
> > __________________________________________________________
> >
约�&#65533;说�&#65533;�&#65533;�&#65533;��&#65533;��&#65533;�&#65533;��&#\
65533;�&#65533;�&#65533;软�&#65533;��&#65533;��&#65533;&#65533;�&#65533;�msn�\
�&#65533;�&#65533;��&#65533;&#65533;�&#65533;��&#65533;
> > http://ditu.live.com/?form=TL&swm=1
> >
> > [Non-text portions of this message have been removed]
> >
> >
> >
> >
> >
> > _________________________________________________________________
> >
约�&#65533;说�&#65533;�&#65533;�&#65533;��&#65533;��&#65533;�&#65533;��&#\
65533;�&#65533;�&#65533;软�&#65533;��&#65533;��&#65533;&#65533;�&#65533;�msn�\
�&#65533;�&#65533;��&#65533;&#65533;�&#65533;��&#65533;
> > http://ditu.live.com/?form=TL&swm=1
> >
> > [Non-text portions of this message have been removed]
> >
>

Hi



I think the problem is the testbench.mpf file is not generated. How about yours?
In my working directory, there is only a tmp.mpf generated which is not the
expected one. I tried to run it on my labmate's environment, the same flow works
well. So i guess it is the problem of the current pc environment, maybe gcc or
msys. I am trying to fix it. If i have any result i will let you know.



vv



To: leon_sparc@yahoogroups.com
From: jarvanitakis@...
Date: Mon, 16 Nov 2009 23:30:47 +0000
Subject: [leon_sparc] Re: make vsim





Hi,

i have the same problem when i try to make vsim...I also noticed that the
"manual" from Lutz Buttelmann thats uploaded on the group has the same error on
the report...

Is there anyway that we can fix it?

thanks,
John

--- In leon_sparc@yahoogroups.com, å¼ ä¹&#65533;ç»´ <yiwei.zhang@...>
wrote:
>
>
> Hi Jiri,
>
>
>
> also, I tried to run it directly under the path of
`../grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800', using original
files from the unzip pack. in this case, make script works well ,report:
>
>
> [eexyz@een5021 leon3-xilinx-xc3sd-1800]$ make scripts
> Scanning libraries
> grlib: stdlib util sparc modgen amba
> unisim: ise
> dw02: comp
> synplify: sim
> techmap: gencomp inferred dw02 unisim maps
> eth: comp core wrapper
> gaisler: arith memctrl leon3 misc net uart sim jtag greth ddr
> esa: memoryctrl
> fmf: utilities flash fifo
> spansion: flash
> gsi: ssram
> cypress: ssram
> hynix: ddr2
> micron: sdram ddr
> work: debug
>
> leon3mp_synplify.prj
> leon3mp_dc.tcl
> leon3mp.rc
> leon3mp.xst
>
>
> ---------------
>
>
>
> but after that, when i run 'make vsim', it reports:
>
>
>
> [eexyz@een5021 leon3-xilinx-xc3sd-1800]$ make vsim
> Reading /app/modelsim64/modeltech/tcl/vsim/pref.tcl
>
> # 6.4a
>
> # do libs.do
> # quit
> make[1]: Entering directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
> make[1]: make.vsim: No such file or directory
> make[1]: *** No rule to make target `make.vsim'. Stop.
> make[1]: Leaving directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
> make: *** [make.work] Error 2
>
>
> ----------
>
> but i can see the compile.vsim file has been generated. very strange. Then i
had another go to start modelsim, and run 'do compile.vsim', it reports:
>
>
>
> [modelsim]>> make vsim
> # make[1]: Entering directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
> # make[1]: Leaving directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
> # make[1]: make.vsim: No such file or directory
> # make[1]: *** No rule to make target `make.vsim'. Stop.
> # make: *** [make.work] Error 2
>
>
> [modelsim]>> do compile.vsim
> # ** Error: Library std not found.
> # ** Error: VHDL Compiler exiting
> # ** Error: /app/modelsim64/modeltech/linux_x86_64/vcom failed.
> # Error in macro ./compile.vsim line 1
> # /app/modelsim64/modeltech/linux_x86_64/vcom failed.
> # while executing
> # "vcom -quiet -93 -work grlib ../../lib/grlib/stdlib/version.vhd"
>
>
>
>
>
>
>
> i can see the library list is generated in modelsim but all are empty, since
vcom is not executed correctly. any suggestion? thanks!
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
> To: leon_sparc@yahoogroups.com
> From: yiwei.zhang@...
> Date: Fri, 13 Nov 2009 18:31:26 +0000
> Subject: RE: [leon_sparc] make vsim
>
>
>
>
>
>
> Hi Jiri,
>
>
>
> 1. I am using bshell, all the environment variables are set in the
.bash_profile file
>
>
>
> 2. after make script, it is the makeFile in the design directory:
/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800
>
>
>
> because there is no Makefile in the path:
/grlib-gpl-1.0.21-b3848/boards/xilinx-spa3-dsp1800a, I copy the one in the
'designs' path to the 'boards' path, and point this directory in the 'Make
scripts' script. Any problem to do that? thanks.
>
>
>
> vv
>
>
>
>
>
>
> To: leon_sparc@yahoogroups.com
> From: jiri@...
> Date: Fri, 13 Nov 2009 17:53:10 +0100
> Subject: Re: [leon_sparc] make vsim
>
>
>
>
>
>
> This is not what I asked. Again:
>
> 1. Which shell are you using?
>
> 2. If you do an 'ls' in the design directory, which files do you see after
> doing 'make scripts' ?
>
> Jiri.
>
> å¼ ä¹&#65533;ç»´ wrote:
> > Hi Jiri
> >
> >
> >
> > I am using Linux. the makefile is the one. I modified the GRLIB to the
directory where the grlib locates. Thanks.
> >
> >
> >
> > include .config
> > GRLIB=../../grlib-gpl-1.0.21-b3848
> > TOP=leon3mp
> > BOARD=xilinx-spa3-dsp1800a
> > include Makefile.inc
> > DEVICE=$(PART)-$(PACKAGE)$(SPEED)
> > UCF=$(TOP).ucf
> > ISEMAPOPT=-timing
> > QSF=$(TOP).qsf
> > EFFORT=high
> > XSTOPT=-uc leon3mp.xcf
> > SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option
-write_apr_constraint 0"
> > VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
> > VHDLSIMFILES=testbench.vhd
> > SIMTOP=testbench
> > SDCFILE=default.sdc
> > BITGEN=default.ut
> > CLEAN=soft-clean
> >
> > TECHLIBS = unisim
> >
> > LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
> > tmtc openchip ihp gleichmann opencores usbhc spw
> > DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest can \
> > usb grusbhc spacewire ata haps coremp7 ascs slink spi hcan
> > FILESKIP = grcan.vhd i2cmst.vhd
> >
> > include $(GRLIB)/bin/Makefile
> > include $(GRLIB)/software/leon3/Makefile
> >
> >
> >
> >
> > To: leon_sparc@yahoogroups.com
> > From: jiri@...
> > Date: Fri, 13 Nov 2009 16:53:12 +0100
> > Subject: Re: [leon_sparc] make vsim
> >
> >
> >
> >
> >
> >
> > Which host OS and shell are you using? If you do an 'ls'
> > in the design directory, which files do you see after
> > doing 'make scripts' ?
> >
> > Jiri.
> >
> > vvzmvv wrote:
> >> Hi Jiri,
> >>
> >> I have some probem when running make vsim.
> >> it reports as below. I checked my GNU VERSION by 'make -v', as below.
> >> My grlib is unziped by 'gunzip -c grlib-gpl-1.0.21-b3848.tar.tar | tar xf
-. So i have no idea where is wrong. My modelsim is modelsim SE 6.4. So could
you give me any suggestion? Many thanks!
> >>
> >>
> >> [eexyz@een5021 ~]$ make -v
> >> GNU Make 3.80
> >> Copyright (C) 2002 Free Software Foundation, Inc.
> >> This is free software; see the source for copying conditions.
> >> There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A
> >> PARTICULAR PURPOSE.
> >>
> >>
> >> ---------------------------------------------
> >>
> >> [eexyz@een5021 leon3-xilinx-xc3sd-1800]$ make scripts
> >> Scanning libraries
> >> grlib: stdlib util sparc modgen amba
> >> unisim: ise
> >> dw02: comp
> >> synplify: sim
> >> techmap: gencomp inferred dw02 unisim maps
> >> eth: comp core wrapper
> >> gaisler: arith memctrl leon3 misc net uart sim jtag greth ddr
> >> esa: memoryctrl
> >> fmf: utilities flash fifo
> >> spansion: flash
> >> gsi: ssram
> >> cypress: ssram
> >> hynix: ddr2
> >> micron: sdram ddr
> >> work: debug
> >>
> >> leon3mp_synplify.prj
> >> leon3mp_dc.tcl
> >> leon3mp.rc
> >> leon3mp.xst
> >> [eexyz@een5021 leon3-xilinx-xc3sd-1800]$ make vsim
> >> Reading /app/modelsim64/modeltech/tcl/vsim/pref.tcl
> >>
> >> # 6.4a
> >>
> >> # do libs.do
> >> # quit
> >> make[1]: Entering directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
> >> make[1]: make.vsim: No such file or directory
> >> make[1]: *** No rule to make target `make.vsim'. Stop.
> >> make[1]: Leaving directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
> >> make: *** [make.work] Error 2
> >>
> >> ----------------------------------
> >>
> >> thanks!
> >>
> >> vv
> >>
> >>
> >>
> >> ------------------------------------
> >>
> >> Yahoo! Groups Links
> >>
> >>
> >>
> >>
> >
> >
> >
> >
> > __________________________________________________________
> >
MSNå&#65533;&#65533;å&#65533;¨å¹´åº&#65533;å&#65533;¸ï¼&#65533;æ&#6\
5533;¥ç&#65533;&#65533;MSN注å&#65533;&#65533;æ&#65533;¶é&#65533;´ï¼\
&#65533;èµ¢å&#65533;&#65533;ç¥&#65533;ç§&#65533;大å¥&#65533;
> > http://10.msn.com.cn
> >
> > [Non-text portions of this message have been removed]
> >
> >
> >
> > ------------------------------------
> >
> > Yahoo! Groups Links
> >
> >
> >
> >
> >
>
>
>
>
> __________________________________________________________
>
约ä¼&#65533;说ä¸&#65533;æ¸&#65533;å&#65533;°æ&#65533;¹ï¼&#65\
533;æ&#65533;¥è¯&#65533;è¯&#65533;å¾&#65533;软å&#65533;°å&#65533;\
¾æ&#65533;&#65533;æ&#65533;°msnäº&#65533;å&#65533;¨å&#65533;&#65533;è&\
#65533;½ï¼&#65533;
> http://ditu.live.com/?form=TL&swm=1
>
> [Non-text portions of this message have been removed]
>
>
>
>
>
> __________________________________________________________
>
约ä¼&#65533;说ä¸&#65533;æ¸&#65533;å&#65533;°æ&#65533;¹ï¼&#65\
533;æ&#65533;¥è¯&#65533;è¯&#65533;å¾&#65533;软å&#65533;°å&#65533;\
¾æ&#65533;&#65533;æ&#65533;°msnäº&#65533;å&#65533;¨å&#65533;&#65533;è&\
#65533;½ï¼&#65533;
> http://ditu.live.com/?form=TL&swm=1
>
> [Non-text portions of this message have been removed]
>





_________________________________________________________________
上Windows Live 中国首页，下载Messenger2009安全版！
http://www.windowslive.cn

[Non-text portions of this message have been removed]

Hi,
You don't need to recompile the entire toolchain. Create a new linker
script in your project directory, lets say linker.ld. This contains
your modified version of the default linker script.
You can than override gcc's default linker script  in your makefile
with something like that:

$(CC) -Xlinker -T linker.ld -o firmware $(OBJFILES)

-Philip

On Nov 16, 2009, at 11:03 PM, Andre wrote:

> Phillip (or Jiri if he knows),
>
> How can I define other without recompile the toolchain? I edited
> the .x* files in sparc-elf/lib/ldscripts and no success.
>
> André
>
> --- In leon_sparc@yahoogroups.com, "Andre" <exotiko@...> wrote:
> >
> > Thank you so much Jiri and Phillip to help me out.
> >
> > Regards,
> > Andr∂«± Luiz.
> >
> > --- In leon_sparc@yahoogroups.com, Philip Axer <axer@> wrote:
> > >
> > > Hi,
> > > just for your convenience: the default linker script can be
> retrieved by
> > > sparc-elf-ld -vebose
> > > You can than modify and add segments by hand.
> > >
> > > Cheers,
> > > Philip
> > >
> > > On Sat, 2009-11-14 at 18:10 +0100, Jiri Gaisler wrote:
> > > >
> > > >
> > > > You need to create a custom link script for gcc that defines
> RAM in
> > > > your area.
> > > > See the gcc docs for details. The default BCC link scripts has
> RAM in
> > > > 0x40000000 - 0xC0000000 .
> > > >
> > > > Jiri.
> > > >
> > > > Andre wrote:
> > > > > Hello, Jiri.
> > > > >
> > > > > I'm using BCC for Leon3. The memory that will run the app is
> at
> > > > 0x10000000 but i can't compile with that address as text area.
> > > > >
> > > > > Can you give me any help?
> > > > >
> > > > > --- In leon_sparc@yahoogroups.com, Jiri Gaisler <jiri@> wrote:
> > > > >>
> > > > >> Which tool-chain are you using and for which leon version/
> device ?
> > > > >>
> > > > >> Jiri.
> > > > >>
> > > > >> Andre wrote:
> > > > >>> Why can't I creat an application with the instruction area
> > > > (-Ttext) between 0x1000000 and
> > > > >>> 0x3fffffff? The Leon i used has a flash memory on
> 0x10000000 bus
> > > > and i doesn't run because of
> > > > >>> that.
> > > > >>>
> > > > >>>
> > > > >>>
> > > > >>> ------------------------------------
> > > > >>>
> > > > >>> Yahoo! Groups Links
> > > > >>>
> > > > >>>
> > > > >
> > > > >
> > > > >
> > > > >
> > > > > ------------------------------------
> > > > >
> > > > > Yahoo! Groups Links
> > > > >
> > > > >
> > > > >
> > > > >
> > > >
> > > >
> > > >
> > > >
> > >
> > >
> > > --
> > > Dipl.-Ing. Philip Axer
> > > Institut f∂ªª&#188;r Datentechnik und Kommunikationsnetze
> > > Hans-Sommer-Stra∂ªª∂ªóe 66 38106 Braunschweig
> > > Tel +49 (531) 391 9662 Fax +49 (531) 391 4587
> > >
> > >
> > > [Non-text portions of this message have been removed]
> > >
> >
>
>



[Non-text portions of this message have been removed]

Hi,

i would like to know what the testbench in designs/leon-gr-xc1500s/testbench.vhd
do...how does it test the processor and what dsucom process do?where can i find
what txc(...,...,...) txa and txp do?

Thanks in advance,
John

Hi,

i have the same problem when i try to make vsim...I also noticed that the
"manual" from Lutz Buttelmann thats uploaded on the group has the same error on
the report...

Is there anyway that we can fix it?

thanks,
John

--- In leon_sparc@yahoogroups.com, 张�&#65533;维 <yiwei.zhang@...> wrote:
>
>
> Hi Jiri,
>
>
>
> also, I tried to run it directly under the path of
`../grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800', using original
files from the unzip pack. in this case, make script works well ,report:
>
>
> [eexyz@een5021 leon3-xilinx-xc3sd-1800]$ make scripts
> Scanning libraries
>   grlib: stdlib util sparc modgen amba
>   unisim: ise
>   dw02: comp
>   synplify: sim
>   techmap: gencomp inferred dw02 unisim maps
>   eth: comp core wrapper
>   gaisler: arith memctrl leon3 misc net uart sim jtag greth ddr
>   esa: memoryctrl
>   fmf: utilities flash fifo
>   spansion: flash
>   gsi: ssram
>   cypress: ssram
>   hynix: ddr2
>   micron: sdram ddr
>   work: debug
>
> leon3mp_synplify.prj
> leon3mp_dc.tcl
> leon3mp.rc
> leon3mp.xst
>
>
> ---------------
>
>
>
> but after that, when i run 'make vsim', it reports:
>
>
>
> [eexyz@een5021 leon3-xilinx-xc3sd-1800]$ make vsim
> Reading /app/modelsim64/modeltech/tcl/vsim/pref.tcl
>
> # 6.4a
>
> # do libs.do
> #  quit
> make[1]: Entering directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
> make[1]: make.vsim: No such file or directory
> make[1]: *** No rule to make target `make.vsim'.  Stop.
> make[1]: Leaving directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
> make: *** [make.work] Error 2
>
>
> ----------
>
> but i can see the compile.vsim file has been generated. very strange. Then i
had another go to start modelsim, and run 'do compile.vsim', it reports:
>
>
>
> [modelsim]>> make vsim
> # make[1]: Entering directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
> # make[1]: Leaving directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
> # make[1]: make.vsim: No such file or directory
> # make[1]: *** No rule to make target `make.vsim'.  Stop.
> # make: *** [make.work] Error 2
>
>
> [modelsim]>> do compile.vsim
> # ** Error: Library std not found.
> # ** Error: VHDL Compiler exiting
> # ** Error: /app/modelsim64/modeltech/linux_x86_64/vcom failed.
> # Error in macro ./compile.vsim line 1
> # /app/modelsim64/modeltech/linux_x86_64/vcom failed.
> #     while executing
> # "vcom -quiet  -93 -work  grlib ../../lib/grlib/stdlib/version.vhd"
>
>
>
>
>
>
>
> i can see the library list is generated in modelsim but all are empty, since
vcom is not executed correctly. any suggestion? thanks!
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
> To: leon_sparc@yahoogroups.com
> From: yiwei.zhang@...
> Date: Fri, 13 Nov 2009 18:31:26 +0000
> Subject: RE: [leon_sparc] make vsim
>
>
>
>
>
>
> Hi Jiri,
>
>
>
> 1. I am using bshell, all the environment variables are set in the
.bash_profile file
>
>
>
> 2. after make script, it is the makeFile in the design directory:
/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800
>
>
>
> because there is no Makefile in the path:
/grlib-gpl-1.0.21-b3848/boards/xilinx-spa3-dsp1800a, I copy the one in the
'designs' path to the 'boards' path, and point this directory in the 'Make
scripts' script. Any problem to do that? thanks.
>
>
>
> vv
>
>
>
>
>
>
> To: leon_sparc@yahoogroups.com
> From: jiri@...
> Date: Fri, 13 Nov 2009 17:53:10 +0100
> Subject: Re: [leon_sparc] make vsim
>
>
>
>
>
>
> This is not what I asked. Again:
>
> 1. Which shell are you using?
>
> 2. If you do an 'ls' in the design directory, which files do you see after
> doing 'make scripts' ?
>
> Jiri.
>
> 张�&#65533;维 wrote:
> > Hi Jiri
> >
> >
> >
> > I am using Linux. the makefile is the one. I modified the GRLIB to the
directory where the grlib locates. Thanks.
> >
> >
> >
> > include .config
> > GRLIB=../../grlib-gpl-1.0.21-b3848
> > TOP=leon3mp
> > BOARD=xilinx-spa3-dsp1800a
> > include Makefile.inc
> > DEVICE=$(PART)-$(PACKAGE)$(SPEED)
> > UCF=$(TOP).ucf
> > ISEMAPOPT=-timing
> > QSF=$(TOP).qsf
> > EFFORT=high
> > XSTOPT=-uc leon3mp.xcf
> > SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option
-write_apr_constraint 0"
> > VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
> > VHDLSIMFILES=testbench.vhd
> > SIMTOP=testbench
> > SDCFILE=default.sdc
> > BITGEN=default.ut
> > CLEAN=soft-clean
> >
> > TECHLIBS = unisim
> >
> > LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
> > tmtc openchip ihp gleichmann opencores usbhc spw
> > DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest can \
> > usb grusbhc spacewire ata haps coremp7 ascs slink spi hcan
> > FILESKIP = grcan.vhd i2cmst.vhd
> >
> > include $(GRLIB)/bin/Makefile
> > include $(GRLIB)/software/leon3/Makefile
> >
> >
> >
> >
> > To: leon_sparc@yahoogroups.com
> > From: jiri@...
> > Date: Fri, 13 Nov 2009 16:53:12 +0100
> > Subject: Re: [leon_sparc] make vsim
> >
> >
> >
> >
> >
> >
> > Which host OS and shell are you using? If you do an 'ls'
> > in the design directory, which files do you see after
> > doing 'make scripts' ?
> >
> > Jiri.
> >
> > vvzmvv wrote:
> >> Hi Jiri,
> >>
> >> I have some probem when running make vsim.
> >> it reports as below. I checked my GNU VERSION by 'make -v', as below.
> >> My grlib is unziped by 'gunzip -c grlib-gpl-1.0.21-b3848.tar.tar | tar xf
-. So i have no idea where is wrong. My modelsim is modelsim SE 6.4. So could
you give me any suggestion? Many thanks!
> >>
> >>
> >> [eexyz@een5021 ~]$ make -v
> >> GNU Make 3.80
> >> Copyright (C) 2002 Free Software Foundation, Inc.
> >> This is free software; see the source for copying conditions.
> >> There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A
> >> PARTICULAR PURPOSE.
> >>
> >>
> >> ---------------------------------------------
> >>
> >> [eexyz@een5021 leon3-xilinx-xc3sd-1800]$ make scripts
> >> Scanning libraries
> >> grlib: stdlib util sparc modgen amba
> >> unisim: ise
> >> dw02: comp
> >> synplify: sim
> >> techmap: gencomp inferred dw02 unisim maps
> >> eth: comp core wrapper
> >> gaisler: arith memctrl leon3 misc net uart sim jtag greth ddr
> >> esa: memoryctrl
> >> fmf: utilities flash fifo
> >> spansion: flash
> >> gsi: ssram
> >> cypress: ssram
> >> hynix: ddr2
> >> micron: sdram ddr
> >> work: debug
> >>
> >> leon3mp_synplify.prj
> >> leon3mp_dc.tcl
> >> leon3mp.rc
> >> leon3mp.xst
> >> [eexyz@een5021 leon3-xilinx-xc3sd-1800]$ make vsim
> >> Reading /app/modelsim64/modeltech/tcl/vsim/pref.tcl
> >>
> >> # 6.4a
> >>
> >> # do libs.do
> >> # quit
> >> make[1]: Entering directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
> >> make[1]: make.vsim: No such file or directory
> >> make[1]: *** No rule to make target `make.vsim'. Stop.
> >> make[1]: Leaving directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
> >> make: *** [make.work] Error 2
> >>
> >> ----------------------------------
> >>
> >> thanks!
> >>
> >> vv
> >>
> >>
> >>
> >> ------------------------------------
> >>
> >> Yahoo! Groups Links
> >>
> >>
> >>
> >>
> >
> >
> >
> >
> > __________________________________________________________
> >
MSN�&#65533;&#65533;�&#65533;�年�&#65533;�&#65533;��&#65533;�&#65533;��&#6553\
3;&#65533;MSN注�&#65533;&#65533;�&#65533;��&#65533;��&#65533;赢�&#65533;&#655\
33;�&#65533;�&#65533;大�&#65533;
> > http://10.msn.com.cn
> >
> > [Non-text portions of this message have been removed]
> >
> >
> >
> > ------------------------------------
> >
> > Yahoo! Groups Links
> >
> >
> >
> >
> >
>
>
>
>
> __________________________________________________________
>
约�&#65533;说�&#65533;�&#65533;�&#65533;��&#65533;��&#65533;�&#65533;��&#\
65533;�&#65533;�&#65533;软�&#65533;��&#65533;��&#65533;&#65533;�&#65533;�msn�\
�&#65533;�&#65533;��&#65533;&#65533;�&#65533;��&#65533;
> http://ditu.live.com/?form=TL&swm=1
>
> [Non-text portions of this message have been removed]
>
>
>
>
>
> _________________________________________________________________
>
约�&#65533;说�&#65533;�&#65533;�&#65533;��&#65533;��&#65533;�&#65533;��&#\
65533;�&#65533;�&#65533;软�&#65533;��&#65533;��&#65533;&#65533;�&#65533;�msn�\
�&#65533;�&#65533;��&#65533;&#65533;�&#65533;��&#65533;
> http://ditu.live.com/?form=TL&swm=1
>
> [Non-text portions of this message have been removed]
>

Phillip (or Jiri if he knows),

How can I define other without recompile the toolchain? I edited the .x* files
in sparc-elf/lib/ldscripts and no success.

Andr�

--- In leon_sparc@yahoogroups.com, "Andre" <exotiko@...> wrote:
>
> Thank you so much Jiri and Phillip to help me out.
>
> Regards,
> Andr��� Luiz.
>
> --- In leon_sparc@yahoogroups.com, Philip Axer <axer@> wrote:
> >
> > Hi,
> > just for your convenience: the default linker script can be retrieved by
> > sparc-elf-ld -vebose
> > You can than modify and add segments by hand.
> >
> > Cheers,
> > Philip
> >
> > On Sat, 2009-11-14 at 18:10 +0100, Jiri Gaisler wrote:
> > >
> > >
> > > You need to create a custom link script for gcc that defines RAM in
> > > your area.
> > > See the gcc docs for details. The default BCC link scripts has RAM in
> > > 0x40000000 - 0xC0000000 .
> > >
> > > Jiri.
> > >
> > > Andre wrote:
> > > > Hello, Jiri.
> > > >
> > > > I'm using BCC for Leon3. The memory that will run the app is at
> > > 0x10000000 but i can't compile with that address as text area.
> > > >
> > > > Can you give me any help?
> > > >
> > > > --- In leon_sparc@yahoogroups.com, Jiri Gaisler <jiri@> wrote:
> > > >>
> > > >> Which tool-chain are you using and for which leon version/device ?
> > > >>
> > > >> Jiri.
> > > >>
> > > >> Andre wrote:
> > > >>> Why can't I creat an application with the instruction area
> > > (-Ttext) between 0x1000000 and
> > > >>> 0x3fffffff? The Leon i used has a flash memory on 0x10000000 bus
> > > and i doesn't run because of
> > > >>> that.
> > > >>>
> > > >>>
> > > >>>
> > > >>> ------------------------------------
> > > >>>
> > > >>> Yahoo! Groups Links
> > > >>>
> > > >>>
> > > >
> > > >
> > > >
> > > >
> > > > ------------------------------------
> > > >
> > > > Yahoo! Groups Links
> > > >
> > > >
> > > >
> > > >
> > >
> > >
> > >
> > >
> >
> >
> > --
> > Dipl.-Ing. Philip Axer
> > Institut f���&#188;r Datentechnik und Kommunikationsnetze
> > Hans-Sommer-Stra������e 66          38106 Braunschweig
> > Tel +49 (531) 391 9662     Fax +49 (531) 391 4587
> >
> >
> > [Non-text portions of this message have been removed]
> >
>

�hello Sir,
�I want to verify leon3 based SoC. i.e functional verification,code coverage
analysis.there is no any example in verification��of grlib.I have Modelsim�SE
6.1C version simulator.�Is there any tutorial regarding code coverage and
functional coverage.
�
�
�
�
Regards,
CHINTAN PATEL
M-TECH VLSI DESIGN




[Non-text portions of this message have been removed]

devox84 wrote:
> Hi Jan,
>
> Thanks for your reply :)
>
> By saying "performing AMBA read and write" you mean SPARC load and store
instructions?? or is there another way?

When performing memory accesses directly from your application; yes I
mean SPARC load and store instructions.

Best regards,
    Jan

Hi Jan,

Thanks for your reply :)

By saying "performing AMBA read and write" you mean SPARC load and store
instructions?? or is there another way?

Regards,
Mahmoud

--- In leon_sparc@yahoogroups.com, Jan Andersson <jan@...> wrote:
>
> The manual describes what the DDR controller core does for you ("An AHB
> read access to the controller will cause a corresponding access to the
> external DDR RAM. ..."). You do not need to issue these commands. Just
> perform AMBA read and writes to the controller memory area..
>
> Best regards,
>    Jan
>
> devox84 wrote:
> > Can someone help me please????
> >
> > --- In leon_sparc@yahoogroups.com, "devox84" <eljammali_mahmoud@> wrote:
> >> Hi all,
> >>
> >> While i was reading in grip manual, DDR2SPA section, in the "Read cycles",
it tell that if i want to read i have to perform  ACTIVATE command and then READ
command. Where i perform theas commands???
> >> Does they have a value like "AUTO-REFRESH" SDRAM command? and where should
i write it??
> >>
> >> Thanks :)
>

The manual describes what the DDR controller core does for you ("An AHB
read access to the controller will cause a corresponding access to the
external DDR RAM. ..."). You do not need to issue these commands. Just
perform AMBA read and writes to the controller memory area..

Best regards,
    Jan

devox84 wrote:
> Can someone help me please????
>
> --- In leon_sparc@yahoogroups.com, "devox84" <eljammali_mahmoud@...> wrote:
>> Hi all,
>>
>> While i was reading in grip manual, DDR2SPA section, in the "Read cycles", it
tell that if i want to read i have to perform  ACTIVATE command and then READ
command. Where i perform theas commands???
>> Does they have a value like "AUTO-REFRESH" SDRAM command? and where should i
write it??
>>
>> Thanks :)

Thank you so much Jiri and Phillip to help me out.

Regards,
Andr��� Luiz.

--- In leon_sparc@yahoogroups.com, Philip Axer <axer@...> wrote:
>
> Hi,
> just for your convenience: the default linker script can be retrieved by
> sparc-elf-ld -vebose
> You can than modify and add segments by hand.
>
> Cheers,
> Philip
>
> On Sat, 2009-11-14 at 18:10 +0100, Jiri Gaisler wrote:
> >
> >
> > You need to create a custom link script for gcc that defines RAM in
> > your area.
> > See the gcc docs for details. The default BCC link scripts has RAM in
> > 0x40000000 - 0xC0000000 .
> >
> > Jiri.
> >
> > Andre wrote:
> > > Hello, Jiri.
> > >
> > > I'm using BCC for Leon3. The memory that will run the app is at
> > 0x10000000 but i can't compile with that address as text area.
> > >
> > > Can you give me any help?
> > >
> > > --- In leon_sparc@yahoogroups.com, Jiri Gaisler <jiri@> wrote:
> > >>
> > >> Which tool-chain are you using and for which leon version/device ?
> > >>
> > >> Jiri.
> > >>
> > >> Andre wrote:
> > >>> Why can't I creat an application with the instruction area
> > (-Ttext) between 0x1000000 and
> > >>> 0x3fffffff? The Leon i used has a flash memory on 0x10000000 bus
> > and i doesn't run because of
> > >>> that.
> > >>>
> > >>>
> > >>>
> > >>> ------------------------------------
> > >>>
> > >>> Yahoo! Groups Links
> > >>>
> > >>>
> > >
> > >
> > >
> > >
> > > ------------------------------------
> > >
> > > Yahoo! Groups Links
> > >
> > >
> > >
> > >
> >
> >
> >
> >
>
>
> --
> Dipl.-Ing. Philip Axer
> Institut f���&#188;r Datentechnik und Kommunikationsnetze
> Hans-Sommer-Stra������e 66          38106 Braunschweig
> Tel +49 (531) 391 9662     Fax +49 (531) 391 4587
>
>
> [Non-text portions of this message have been removed]
>

Hi,
just for your convenience: the default linker script can be retrieved by
sparc-elf-ld -vebose
You can than modify and add segments by hand.

Cheers,
Philip

On Sat, 2009-11-14 at 18:10 +0100, Jiri Gaisler wrote:
>
>
> You need to create a custom link script for gcc that defines RAM in
> your area.
> See the gcc docs for details. The default BCC link scripts has RAM in
> 0x40000000 - 0xC0000000 .
>
> Jiri.
>
> Andre wrote:
> > Hello, Jiri.
> >
> > I'm using BCC for Leon3. The memory that will run the app is at
> 0x10000000 but i can't compile with that address as text area.
> >
> > Can you give me any help?
> >
> > --- In leon_sparc@yahoogroups.com, Jiri Gaisler <jiri@...> wrote:
> >>
> >> Which tool-chain are you using and for which leon version/device ?
> >>
> >> Jiri.
> >>
> >> Andre wrote:
> >>> Why can't I creat an application with the instruction area
> (-Ttext) between 0x1000000 and
> >>> 0x3fffffff? The Leon i used has a flash memory on 0x10000000 bus
> and i doesn't run because of
> >>> that.
> >>>
> >>>
> >>>
> >>> ------------------------------------
> >>>
> >>> Yahoo! Groups Links
> >>>
> >>>
> >
> >
> >
> >
> > ------------------------------------
> >
> > Yahoo! Groups Links
> >
> >
> >
> >
>
>
>
>


--
Dipl.-Ing. Philip Axer
Institut für Datentechnik und Kommunikationsnetze
Hans-Sommer-Straße 66          38106 Braunschweig
Tel +49 (531) 391 9662     Fax +49 (531) 391 4587


[Non-text portions of this message have been removed]

Can someone help me please????

--- In leon_sparc@yahoogroups.com, "devox84" <eljammali_mahmoud@...> wrote:
>
> Hi all,
>
> While i was reading in grip manual, DDR2SPA section, in the "Read cycles", it
tell that if i want to read i have to perform  ACTIVATE command and then READ
command. Where i perform theas commands???
> Does they have a value like "AUTO-REFRESH" SDRAM command? and where should i
write it??
>
> Thanks :)
>

You need to create a custom link script for gcc that defines RAM in your area.
See the gcc docs for details. The default BCC link scripts has RAM in
0x40000000 - 0xC0000000 .

Jiri.

Andre wrote:
> Hello, Jiri.
>
> I'm using BCC for Leon3. The memory that will run the app is at 0x10000000 but
i can't compile with that address as text area.
>
> Can you give me any help?
>
> --- In leon_sparc@yahoogroups.com, Jiri Gaisler <jiri@...> wrote:
>>
>> Which tool-chain are you using and for which leon version/device ?
>>
>> Jiri.
>>
>> Andre wrote:
>>> Why can't I creat an application with the instruction area (-Ttext) between
0x1000000 and
>>> 0x3fffffff? The Leon i used has a flash memory on 0x10000000 bus and i
doesn't run because of
>>> that.
>>>
>>>
>>>
>>> ------------------------------------
>>>
>>> Yahoo! Groups Links
>>>
>>>
>
>
>
>
> ------------------------------------
>
> Yahoo! Groups Links
>
>
>
>

Hi all,

While i was reading in grip manual, DDR2SPA section, in the "Read cycles", it
tell that if i want to read i have to perform  ACTIVATE command and then READ
command. Where i perform theas commands???
Does they have a value like "AUTO-REFRESH" SDRAM command? and where should i
write it??

Thanks :)

Hi Philip,

Thanks for your reply.
I found a usfull informatin there :)

--- In leon_sparc@yahoogroups.com, Philip Axer <axer@...> wrote:
>
> Hi Eljammali,
> first off, I assume you are using the sources provided by gaisler
> research as they are.
> Check the grgpio section in the grip manual and be sure you have
> enabled gpio in your configuration and the pins are wired correctly
> (check your constraints file). You can than use mmio to access the
> gpio core to write/read from/to the pins that you have assigned to the
> gpio port.
>
> Cheers,
> -Philip
>
>
> check the gpio
> On Nov 6, 2009, at 8:04 PM, devox84 wrote:
>
> > Isn't there anyone who know how to do it???
> >
> > --- In leon_sparc@yahoogroups.com, "devox84" <eljammali_mahmoud@>
> > wrote:
> > >
> > > Hi everyone,
> > >
> > > I want to write a simple C program to do the following:
> > > the program has a counter (0-15) and this counter value is
> > reflected on 4 LEDs in the board. and 2 buttons, one for increase
> > and one for decrease.
> > >
> > > what are the documents i have to read to do so???
> > > and if possible, give me some hints about what to read in these
> > documents.
> > >
> > > I am actually trying to understand how the C program are going to
> > know where is the LEDs and the buttons and how to interface with them.
> > >
> > > i tried allot but didn't get the answer.
> > > Thanks.
> > >
> >
> >
>
>
>
> [Non-text portions of this message have been removed]
>

Hello, Jiri.

I'm using BCC for Leon3. The memory that will run the app is at 0x10000000 but i
can't compile with that address as text area.

Can you give me any help?

--- In leon_sparc@yahoogroups.com, Jiri Gaisler <jiri@...> wrote:
>
>
> Which tool-chain are you using and for which leon version/device ?
>
> Jiri.
>
> Andre wrote:
> > Why can't I creat an application with the instruction area (-Ttext) between
0x1000000 and
> > 0x3fffffff? The Leon i used has a flash memory on 0x10000000 bus and i
doesn't run because of
> > that.
> >
> >
> >
> > ------------------------------------
> >
> > Yahoo! Groups Links
> >
> >
>

Hi Jiri,



also, I tried to run it directly under the path of
`../grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800', using original
files from the unzip pack. in this case, make script works well ,report:


[eexyz@een5021 leon3-xilinx-xc3sd-1800]$ make scripts
Scanning libraries
   grlib: stdlib util sparc modgen amba
   unisim: ise
   dw02: comp
   synplify: sim
   techmap: gencomp inferred dw02 unisim maps
   eth: comp core wrapper
   gaisler: arith memctrl leon3 misc net uart sim jtag greth ddr
   esa: memoryctrl
   fmf: utilities flash fifo
   spansion: flash
   gsi: ssram
   cypress: ssram
   hynix: ddr2
   micron: sdram ddr
   work: debug

leon3mp_synplify.prj
leon3mp_dc.tcl
leon3mp.rc
leon3mp.xst


---------------



but after that, when i run 'make vsim', it reports:



[eexyz@een5021 leon3-xilinx-xc3sd-1800]$ make vsim
Reading /app/modelsim64/modeltech/tcl/vsim/pref.tcl

# 6.4a

# do libs.do
#  quit
make[1]: Entering directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
make[1]: make.vsim: No such file or directory
make[1]: *** No rule to make target `make.vsim'.  Stop.
make[1]: Leaving directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
make: *** [make.work] Error 2


----------

but i can see the compile.vsim file has been generated. very strange. Then i had
another go to start modelsim, and run 'do compile.vsim', it reports:



[modelsim]>> make vsim
# make[1]: Entering directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
# make[1]: Leaving directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
# make[1]: make.vsim: No such file or directory
# make[1]: *** No rule to make target `make.vsim'.  Stop.
# make: *** [make.work] Error 2


[modelsim]>> do compile.vsim
# ** Error: Library std not found.
# ** Error: VHDL Compiler exiting
# ** Error: /app/modelsim64/modeltech/linux_x86_64/vcom failed.
# Error in macro ./compile.vsim line 1
# /app/modelsim64/modeltech/linux_x86_64/vcom failed.
#     while executing
# "vcom -quiet  -93 -work  grlib ../../lib/grlib/stdlib/version.vhd"







i can see the library list is generated in modelsim but all are empty, since
vcom is not executed correctly. any suggestion? thanks!




















To: leon_sparc@yahoogroups.com
From: yiwei.zhang@...
Date: Fri, 13 Nov 2009 18:31:26 +0000
Subject: RE: [leon_sparc] make vsim






Hi Jiri,



1. I am using bshell, all the environment variables are set in the .bash_profile
file



2. after make script, it is the makeFile in the design directory:
/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800



because there is no Makefile in the path:
/grlib-gpl-1.0.21-b3848/boards/xilinx-spa3-dsp1800a, I copy the one in the
'designs' path to the 'boards' path, and point this directory in the 'Make
scripts' script. Any problem to do that? thanks.



vv






To: leon_sparc@yahoogroups.com
From: jiri@...
Date: Fri, 13 Nov 2009 17:53:10 +0100
Subject: Re: [leon_sparc] make vsim






This is not what I asked. Again:

1. Which shell are you using?

2. If you do an 'ls' in the design directory, which files do you see after
doing 'make scripts' ?

Jiri.

张乙维 wrote:
> Hi Jiri
>
>
>
> I am using Linux. the makefile is the one. I modified the GRLIB to the
directory where the grlib locates. Thanks.
>
>
>
> include .config
> GRLIB=../../grlib-gpl-1.0.21-b3848
> TOP=leon3mp
> BOARD=xilinx-spa3-dsp1800a
> include Makefile.inc
> DEVICE=$(PART)-$(PACKAGE)$(SPEED)
> UCF=$(TOP).ucf
> ISEMAPOPT=-timing
> QSF=$(TOP).qsf
> EFFORT=high
> XSTOPT=-uc leon3mp.xcf
> SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option
-write_apr_constraint 0"
> VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
> VHDLSIMFILES=testbench.vhd
> SIMTOP=testbench
> SDCFILE=default.sdc
> BITGEN=default.ut
> CLEAN=soft-clean
>
> TECHLIBS = unisim
>
> LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
> tmtc openchip ihp gleichmann opencores usbhc spw
> DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest can \
> usb grusbhc spacewire ata haps coremp7 ascs slink spi hcan
> FILESKIP = grcan.vhd i2cmst.vhd
>
> include $(GRLIB)/bin/Makefile
> include $(GRLIB)/software/leon3/Makefile
>
>
>
>
> To: leon_sparc@yahoogroups.com
> From: jiri@...
> Date: Fri, 13 Nov 2009 16:53:12 +0100
> Subject: Re: [leon_sparc] make vsim
>
>
>
>
>
>
> Which host OS and shell are you using? If you do an 'ls'
> in the design directory, which files do you see after
> doing 'make scripts' ?
>
> Jiri.
>
> vvzmvv wrote:
>> Hi Jiri,
>>
>> I have some probem when running make vsim.
>> it reports as below. I checked my GNU VERSION by 'make -v', as below.
>> My grlib is unziped by 'gunzip -c grlib-gpl-1.0.21-b3848.tar.tar | tar xf -.
So i have no idea where is wrong. My modelsim is modelsim SE 6.4. So could you
give me any suggestion? Many thanks!
>>
>>
>> [eexyz@een5021 ~]$ make -v
>> GNU Make 3.80
>> Copyright (C) 2002 Free Software Foundation, Inc.
>> This is free software; see the source for copying conditions.
>> There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A
>> PARTICULAR PURPOSE.
>>
>>
>> ---------------------------------------------
>>
>> [eexyz@een5021 leon3-xilinx-xc3sd-1800]$ make scripts
>> Scanning libraries
>> grlib: stdlib util sparc modgen amba
>> unisim: ise
>> dw02: comp
>> synplify: sim
>> techmap: gencomp inferred dw02 unisim maps
>> eth: comp core wrapper
>> gaisler: arith memctrl leon3 misc net uart sim jtag greth ddr
>> esa: memoryctrl
>> fmf: utilities flash fifo
>> spansion: flash
>> gsi: ssram
>> cypress: ssram
>> hynix: ddr2
>> micron: sdram ddr
>> work: debug
>>
>> leon3mp_synplify.prj
>> leon3mp_dc.tcl
>> leon3mp.rc
>> leon3mp.xst
>> [eexyz@een5021 leon3-xilinx-xc3sd-1800]$ make vsim
>> Reading /app/modelsim64/modeltech/tcl/vsim/pref.tcl
>>
>> # 6.4a
>>
>> # do libs.do
>> # quit
>> make[1]: Entering directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
>> make[1]: make.vsim: No such file or directory
>> make[1]: *** No rule to make target `make.vsim'. Stop.
>> make[1]: Leaving directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
>> make: *** [make.work] Error 2
>>
>> ----------------------------------
>>
>> thanks!
>>
>> vv
>>
>>
>>
>> ------------------------------------
>>
>> Yahoo! Groups Links
>>
>>
>>
>>
>
>
>
>
> __________________________________________________________
> MSN十周年庆典，查看MSN注册时间，赢取神秘大奖
> http://10.msn.com.cn
>
> [Non-text portions of this message have been removed]
>
>
>
> ------------------------------------
>
> Yahoo! Groups Links
>
>
>
>
>




__________________________________________________________
约会说不清地方？来试试微软地图最新msn互动功能！
http://ditu.live.com/?form=TL&swm=1

[Non-text portions of this message have been removed]





_________________________________________________________________
约会说不清地方？来试试微软地图最新msn互动功能！
http://ditu.live.com/?form=TL&swm=1

[Non-text portions of this message have been removed]

Hi Jiri,



1. I am using bshell, all the environment variables are set in the .bash_profile
file



2. after make script, it is the makeFile in the design directory:
/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800



because there is no Makefile in the path: 
/grlib-gpl-1.0.21-b3848/boards/xilinx-spa3-dsp1800a, I copy the one in the
'designs' path to the 'boards' path, and point this directory in the 'Make
scripts' script. Any problem to do that? thanks.



vv






To: leon_sparc@yahoogroups.com
From: jiri@...
Date: Fri, 13 Nov 2009 17:53:10 +0100
Subject: Re: [leon_sparc] make vsim






This is not what I asked. Again:

1. Which shell are you using?

2. If you do an 'ls' in the design directory, which files do you see after
doing 'make scripts' ?

Jiri.

张乙维 wrote:
> Hi Jiri
>
>
>
> I am using Linux. the makefile is the one. I modified the GRLIB to the
directory where the grlib locates. Thanks.
>
>
>
> include .config
> GRLIB=../../grlib-gpl-1.0.21-b3848
> TOP=leon3mp
> BOARD=xilinx-spa3-dsp1800a
> include Makefile.inc
> DEVICE=$(PART)-$(PACKAGE)$(SPEED)
> UCF=$(TOP).ucf
> ISEMAPOPT=-timing
> QSF=$(TOP).qsf
> EFFORT=high
> XSTOPT=-uc leon3mp.xcf
> SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option
-write_apr_constraint 0"
> VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
> VHDLSIMFILES=testbench.vhd
> SIMTOP=testbench
> SDCFILE=default.sdc
> BITGEN=default.ut
> CLEAN=soft-clean
>
> TECHLIBS = unisim
>
> LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
> tmtc openchip ihp gleichmann opencores usbhc spw
> DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest can \
> usb grusbhc spacewire ata haps coremp7 ascs slink spi hcan
> FILESKIP = grcan.vhd i2cmst.vhd
>
> include $(GRLIB)/bin/Makefile
> include $(GRLIB)/software/leon3/Makefile
>
>
>
>
> To: leon_sparc@yahoogroups.com
> From: jiri@...
> Date: Fri, 13 Nov 2009 16:53:12 +0100
> Subject: Re: [leon_sparc] make vsim
>
>
>
>
>
>
> Which host OS and shell are you using? If you do an 'ls'
> in the design directory, which files do you see after
> doing 'make scripts' ?
>
> Jiri.
>
> vvzmvv wrote:
>> Hi Jiri,
>>
>> I have some probem when running make vsim.
>> it reports as below. I checked my GNU VERSION by 'make -v', as below.
>> My grlib is unziped by 'gunzip -c grlib-gpl-1.0.21-b3848.tar.tar | tar xf -.
So i have no idea where is wrong. My modelsim is modelsim SE 6.4. So could you
give me any suggestion? Many thanks!
>>
>>
>> [eexyz@een5021 ~]$ make -v
>> GNU Make 3.80
>> Copyright (C) 2002 Free Software Foundation, Inc.
>> This is free software; see the source for copying conditions.
>> There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A
>> PARTICULAR PURPOSE.
>>
>>
>> ---------------------------------------------
>>
>> [eexyz@een5021 leon3-xilinx-xc3sd-1800]$ make scripts
>> Scanning libraries
>> grlib: stdlib util sparc modgen amba
>> unisim: ise
>> dw02: comp
>> synplify: sim
>> techmap: gencomp inferred dw02 unisim maps
>> eth: comp core wrapper
>> gaisler: arith memctrl leon3 misc net uart sim jtag greth ddr
>> esa: memoryctrl
>> fmf: utilities flash fifo
>> spansion: flash
>> gsi: ssram
>> cypress: ssram
>> hynix: ddr2
>> micron: sdram ddr
>> work: debug
>>
>> leon3mp_synplify.prj
>> leon3mp_dc.tcl
>> leon3mp.rc
>> leon3mp.xst
>> [eexyz@een5021 leon3-xilinx-xc3sd-1800]$ make vsim
>> Reading /app/modelsim64/modeltech/tcl/vsim/pref.tcl
>>
>> # 6.4a
>>
>> # do libs.do
>> # quit
>> make[1]: Entering directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
>> make[1]: make.vsim: No such file or directory
>> make[1]: *** No rule to make target `make.vsim'. Stop.
>> make[1]: Leaving directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
>> make: *** [make.work] Error 2
>>
>> ----------------------------------
>>
>> thanks!
>>
>> vv
>>
>>
>>
>> ------------------------------------
>>
>> Yahoo! Groups Links
>>
>>
>>
>>
>
>
>
>
> __________________________________________________________
> MSN十周年庆典，查看MSN注册时间，赢取神秘大奖
> http://10.msn.com.cn
>
> [Non-text portions of this message have been removed]
>
>
>
> ------------------------------------
>
> Yahoo! Groups Links
>
>
>
>
>




_________________________________________________________________
约会说不清地方？来试试微软地图最新msn互动功能！
http://ditu.live.com/?form=TL&swm=1

[Non-text portions of this message have been removed]

This is not what I asked. Again:

1. Which shell are you using?

2. If you do an 'ls' in the design directory, which files do you see after
     doing 'make scripts' ?

Jiri.

张乙维 wrote:
> Hi Jiri
>
>
>
> I am using Linux.  the makefile is the one. I modified the GRLIB to the
directory where the grlib locates. Thanks.
>
>
>
> include .config
> GRLIB=../../grlib-gpl-1.0.21-b3848
> TOP=leon3mp
> BOARD=xilinx-spa3-dsp1800a
> include Makefile.inc
> DEVICE=$(PART)-$(PACKAGE)$(SPEED)
> UCF=$(TOP).ucf
> ISEMAPOPT=-timing
> QSF=$(TOP).qsf
> EFFORT=high
> XSTOPT=-uc leon3mp.xcf
> SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option
-write_apr_constraint 0"
> VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
> VHDLSIMFILES=testbench.vhd
> SIMTOP=testbench
> SDCFILE=default.sdc
> BITGEN=default.ut
> CLEAN=soft-clean
>
> TECHLIBS = unisim
>
> LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
>         tmtc openchip ihp gleichmann opencores usbhc spw
> DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest can \
>         usb grusbhc spacewire ata haps coremp7 ascs slink spi hcan
> FILESKIP = grcan.vhd i2cmst.vhd
>
> include $(GRLIB)/bin/Makefile
> include $(GRLIB)/software/leon3/Makefile
>
>
>
>
> To: leon_sparc@yahoogroups.com
> From: jiri@...
> Date: Fri, 13 Nov 2009 16:53:12 +0100
> Subject: Re: [leon_sparc] make vsim
>
>
>
>
>
>
> Which host OS and shell are you using? If you do an 'ls'
> in the design directory, which files do you see after
> doing 'make scripts' ?
>
> Jiri.
>
> vvzmvv wrote:
>> Hi Jiri,
>>
>> I have some probem when running make vsim.
>> it reports as below. I checked my GNU VERSION by 'make -v', as below.
>> My grlib is unziped by 'gunzip -c grlib-gpl-1.0.21-b3848.tar.tar | tar xf -.
So i have no idea where is wrong. My modelsim is modelsim SE 6.4. So could you
give me any suggestion? Many thanks!
>>
>>
>> [eexyz@een5021 ~]$ make -v
>> GNU Make 3.80
>> Copyright (C) 2002 Free Software Foundation, Inc.
>> This is free software; see the source for copying conditions.
>> There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A
>> PARTICULAR PURPOSE.
>>
>>
>> ---------------------------------------------
>>
>> [eexyz@een5021 leon3-xilinx-xc3sd-1800]$ make scripts
>> Scanning libraries
>> grlib: stdlib util sparc modgen amba
>> unisim: ise
>> dw02: comp
>> synplify: sim
>> techmap: gencomp inferred dw02 unisim maps
>> eth: comp core wrapper
>> gaisler: arith memctrl leon3 misc net uart sim jtag greth ddr
>> esa: memoryctrl
>> fmf: utilities flash fifo
>> spansion: flash
>> gsi: ssram
>> cypress: ssram
>> hynix: ddr2
>> micron: sdram ddr
>> work: debug
>>
>> leon3mp_synplify.prj
>> leon3mp_dc.tcl
>> leon3mp.rc
>> leon3mp.xst
>> [eexyz@een5021 leon3-xilinx-xc3sd-1800]$ make vsim
>> Reading /app/modelsim64/modeltech/tcl/vsim/pref.tcl
>>
>> # 6.4a
>>
>> # do libs.do
>> # quit
>> make[1]: Entering directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
>> make[1]: make.vsim: No such file or directory
>> make[1]: *** No rule to make target `make.vsim'. Stop.
>> make[1]: Leaving directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
>> make: *** [make.work] Error 2
>>
>> ----------------------------------
>>
>> thanks!
>>
>> vv
>>
>>
>>
>> ------------------------------------
>>
>> Yahoo! Groups Links
>>
>>
>>
>>
>
>
>
>
> _________________________________________________________________
> MSN十周年庆典，查看MSN注册时间，赢取神秘大奖
> http://10.msn.com.cn
>
> [Non-text portions of this message have been removed]
>
>
>
> ------------------------------------
>
> Yahoo! Groups Links
>
>
>
>
>

Hi Jiri



I am using Linux.  the makefile is the one. I modified the GRLIB to the
directory where the grlib locates. Thanks.



include .config
GRLIB=../../grlib-gpl-1.0.21-b3848
TOP=leon3mp
BOARD=xilinx-spa3-dsp1800a
include Makefile.inc
DEVICE=$(PART)-$(PACKAGE)$(SPEED)
UCF=$(TOP).ucf
ISEMAPOPT=-timing
QSF=$(TOP).qsf
EFFORT=high
XSTOPT=-uc leon3mp.xcf
SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option
-write_apr_constraint 0"
VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
VHDLSIMFILES=testbench.vhd
SIMTOP=testbench
SDCFILE=default.sdc
BITGEN=default.ut
CLEAN=soft-clean

TECHLIBS = unisim

LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
         tmtc openchip ihp gleichmann opencores usbhc spw
DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest can \
         usb grusbhc spacewire ata haps coremp7 ascs slink spi hcan
FILESKIP = grcan.vhd i2cmst.vhd

include $(GRLIB)/bin/Makefile
include $(GRLIB)/software/leon3/Makefile




To: leon_sparc@yahoogroups.com
From: jiri@...
Date: Fri, 13 Nov 2009 16:53:12 +0100
Subject: Re: [leon_sparc] make vsim






Which host OS and shell are you using? If you do an 'ls'
in the design directory, which files do you see after
doing 'make scripts' ?

Jiri.

vvzmvv wrote:
> Hi Jiri,
>
> I have some probem when running make vsim.
> it reports as below. I checked my GNU VERSION by 'make -v', as below.
> My grlib is unziped by 'gunzip -c grlib-gpl-1.0.21-b3848.tar.tar | tar xf -.
So i have no idea where is wrong. My modelsim is modelsim SE 6.4. So could you
give me any suggestion? Many thanks!
>
>
> [eexyz@een5021 ~]$ make -v
> GNU Make 3.80
> Copyright (C) 2002 Free Software Foundation, Inc.
> This is free software; see the source for copying conditions.
> There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A
> PARTICULAR PURPOSE.
>
>
> ---------------------------------------------
>
> [eexyz@een5021 leon3-xilinx-xc3sd-1800]$ make scripts
> Scanning libraries
> grlib: stdlib util sparc modgen amba
> unisim: ise
> dw02: comp
> synplify: sim
> techmap: gencomp inferred dw02 unisim maps
> eth: comp core wrapper
> gaisler: arith memctrl leon3 misc net uart sim jtag greth ddr
> esa: memoryctrl
> fmf: utilities flash fifo
> spansion: flash
> gsi: ssram
> cypress: ssram
> hynix: ddr2
> micron: sdram ddr
> work: debug
>
> leon3mp_synplify.prj
> leon3mp_dc.tcl
> leon3mp.rc
> leon3mp.xst
> [eexyz@een5021 leon3-xilinx-xc3sd-1800]$ make vsim
> Reading /app/modelsim64/modeltech/tcl/vsim/pref.tcl
>
> # 6.4a
>
> # do libs.do
> # quit
> make[1]: Entering directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
> make[1]: make.vsim: No such file or directory
> make[1]: *** No rule to make target `make.vsim'. Stop.
> make[1]: Leaving directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
> make: *** [make.work] Error 2
>
> ----------------------------------
>
> thanks!
>
> vv
>
>
>
> ------------------------------------
>
> Yahoo! Groups Links
>
>
>
>




_________________________________________________________________
MSN十周年庆典，查看MSN注册时间，赢取神秘大奖
http://10.msn.com.cn

[Non-text portions of this message have been removed]

Which host OS and shell are you using? If you do an 'ls'
in the design directory, which files do you see after
doing 'make scripts' ?

Jiri.

vvzmvv wrote:
> Hi Jiri,
>
> I have some probem when running make vsim.
> it reports as below. I checked my GNU VERSION by 'make -v', as below.
> My grlib is unziped by 'gunzip -c   grlib-gpl-1.0.21-b3848.tar.tar | tar xf -.
So i have no idea where is wrong. My modelsim is modelsim SE 6.4. So could you
give me any suggestion? Many thanks!
>
>
> [eexyz@een5021 ~]$ make -v
> GNU Make 3.80
> Copyright (C) 2002  Free Software Foundation, Inc.
> This is free software; see the source for copying conditions.
> There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A
> PARTICULAR PURPOSE.
>
>
> ---------------------------------------------
>
> [eexyz@een5021 leon3-xilinx-xc3sd-1800]$ make scripts
> Scanning libraries
>   grlib: stdlib util sparc modgen amba
>   unisim: ise
>   dw02: comp
>   synplify: sim
>   techmap: gencomp inferred dw02 unisim maps
>   eth: comp core wrapper
>   gaisler: arith memctrl leon3 misc net uart sim jtag greth ddr
>   esa: memoryctrl
>   fmf: utilities flash fifo
>   spansion: flash
>   gsi: ssram
>   cypress: ssram
>   hynix: ddr2
>   micron: sdram ddr
>   work: debug
>
> leon3mp_synplify.prj
> leon3mp_dc.tcl
> leon3mp.rc
> leon3mp.xst
> [eexyz@een5021 leon3-xilinx-xc3sd-1800]$ make vsim
> Reading /app/modelsim64/modeltech/tcl/vsim/pref.tcl
>
> # 6.4a
>
> # do libs.do
> #  quit
> make[1]: Entering directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
> make[1]: make.vsim: No such file or directory
> make[1]: *** No rule to make target `make.vsim'.  Stop.
> make[1]: Leaving directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
> make: *** [make.work] Error 2
>
> ----------------------------------
>
> thanks!
>
> vv
>
>
>
> ------------------------------------
>
> Yahoo! Groups Links
>
>
>
>

Hi Jiri,

I have some probem when running make vsim.
it reports as below. I checked my GNU VERSION by 'make -v', as below.
My grlib is unziped by 'gunzip -c   grlib-gpl-1.0.21-b3848.tar.tar | tar xf -.
So i have no idea where is wrong. My modelsim is modelsim SE 6.4. So could you
give me any suggestion? Many thanks!


[eexyz@een5021 ~]$ make -v
GNU Make 3.80
Copyright (C) 2002  Free Software Foundation, Inc.
This is free software; see the source for copying conditions.
There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A
PARTICULAR PURPOSE.


---------------------------------------------

[eexyz@een5021 leon3-xilinx-xc3sd-1800]$ make scripts
Scanning libraries
   grlib: stdlib util sparc modgen amba
   unisim: ise
   dw02: comp
   synplify: sim
   techmap: gencomp inferred dw02 unisim maps
   eth: comp core wrapper
   gaisler: arith memctrl leon3 misc net uart sim jtag greth ddr
   esa: memoryctrl
   fmf: utilities flash fifo
   spansion: flash
   gsi: ssram
   cypress: ssram
   hynix: ddr2
   micron: sdram ddr
   work: debug

leon3mp_synplify.prj
leon3mp_dc.tcl
leon3mp.rc
leon3mp.xst
[eexyz@een5021 leon3-xilinx-xc3sd-1800]$ make vsim
Reading /app/modelsim64/modeltech/tcl/vsim/pref.tcl

# 6.4a

# do libs.do
#  quit
make[1]: Entering directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
make[1]: make.vsim: No such file or directory
make[1]: *** No rule to make target `make.vsim'.  Stop.
make[1]: Leaving directory
`/home/eexyz/grlib-gpl-1.0.21-b3848/designs/leon3-xilinx-xc3sd-1800'
make: *** [make.work] Error 2

----------------------------------

thanks!

vv

This is not possible. Use coregen if you need this feature or write
such a module yourself. It is not too difficult, the pre-initialized
data is defined on the generics of the Xilinx RAM blocks.

Jiri.

vvzmvv wrote:
> Hi Jiri,
>
> I wonder if i can initialise a ahbdpram by using a init data file? as what we
do in Xillinx
> coregen. I tried to modify the library, but it does not work. So could you
tell me if it is
> possible? Thanks.
>
> Regards,
>
> vv
>
>
>
> ------------------------------------
>
> Yahoo! Groups Links
>
>

Hi Jiri,

I wonder if i can initialise a ahbdpram by using a init data file? as what we do
in Xillinx coregen. I tried to modify the library, but it does not work. So
could you tell me if it is possible? Thanks.

Regards,

vv

You need to make your own AHB interface. Take a look at AHBDPRAM core
for how this can be done ...

Jiri.

vvzmvv wrote:
> Hi Jiti,
>
> Please skip the previous question. I just saw it is actually two two-port rams
with the
> combination of the write bus. there is no ahb interfaces for the regfile. So i
wonder it can not
> be attached on ahb bus? I have to develop the ahb controller for it myself?
Thanks.
>
> Regards,
>
> vv
>
> --- In leon_sparc@yahoogroups.com, "vvzmvv" <vvzmvv@...> wrote:
>> Hi Jiri,
>>
>> i want to add 'regfile' ipcore in grlib to my design. The doc says it is
actually a three-port
>> ram. the device i am using is xilinx sp3a-dsp-1800a. i checked xilinx
datasheet but only dual
>> port and single port are supported by the fpga, while the grlib file says it
is supported by
>> spartan3 technology. So do you think the regfile can be implemented correctly
on the device?
>> Many thanks!
>>
>> Regards,
>>
>> vv
>>
>
>
>
>
> ------------------------------------
>
> Yahoo! Groups Links
>
>

Hi Jiti,

Please skip the previous question. I just saw it is actually two two-port rams
with the combination of the write bus. there is no ahb interfaces for the
regfile. So i wonder it can not be attached on ahb bus? I have to develop the
ahb controller for it myself? Thanks.

Regards,

vv

--- In leon_sparc@yahoogroups.com, "vvzmvv" <vvzmvv@...> wrote:
>
> Hi Jiri,
>
> i want to add 'regfile' ipcore in grlib to my design. The doc says it is
actually a three-port ram. the device i am using is xilinx sp3a-dsp-1800a. i
checked xilinx datasheet but only dual port and single port are supported by the
fpga, while the grlib file says it is supported by spartan3 technology. So do
you think the regfile can be implemented correctly on the device? Many thanks!
>
> Regards,
>
> vv
>

Hi Jiri,

i want to add 'regfile' ipcore in grlib to my design. The doc says it is
actually a three-port ram. the device i am using is xilinx sp3a-dsp-1800a. i
checked xilinx datasheet but only dual port and single port are supported by the
fpga, while the grlib file says it is supported by spartan3 technology. So do
you think the regfile can be implemented correctly on the device? Many thanks!

Regards,

vv

Hi all,

I hope you can help me.  We are currently developing a system on an
Atmel AT697E processor and have a requirement to be able to trap a data
access exception (trap 0x09) due to a double EDAC error.

We are using the bcc tool chain, and from the reading I've done it
appears that we will need develop our own functions similar to the
lolevelirqinstall() function, as suggested by Jiri Gaisler in an answer
to a previous, similar question in this forum
(http://tech.groups.yahoo.com/group/leon_sparc/message/13830).

The bcc documentation suggests that to do this we will need to "ensure
proper environment setup" before calling our routine (saving volatile
registers, checking for invalid windows and avoiding nested IRQs). There
then follows some example assembly code which may be a way to achieve this.

Is anyone able to give advice (or even better an example!) on how we can
write and register a suitable trap handler?

Thanks in advance,

Regards,

Neil

--

* *

*Neil MacEwen*

*Steepest Ascent Ltd*

*Ladywell**, 94 Duke Street, Glasgow, G4 0UW, UK*

*t**:   +44 (0) 141 552 8855*

*e**:**  **_neil@... <mailto:neil@...>_*

*w**:** **_www.steepestascent.com <http://www.steepestascent.com/>_*





[Non-text portions of this message have been removed]

Now I have run the synthesis with XST as well and can
verify that it is a XST problem. None of the debug links
can access the design when fixed priority is selected.

So your options are to stick with round-robin or use
Synplify instead.

/Marko

Marko Isomaki wrote:
>
>
> I have followed the same procedure you used and it worked
> straight off with both ise 9.2 and 10.1 regardless of the
> arbitration setting. Are you using XST for synthesis? If you did
> that might have caused the problems, I used Synplify 2009-06.
>
> /Marko
>
> Marko Isomaki wrote:
> >
> >
> > Ok, I thought you only had 4 masters enabled (2 x cpu, ahbuart, jtag)
> > but if you only made
> > those changes you mentioned then the GRETH, PCI MTF and CAN must
> > also be enabled. I'll test that configuration too.
> >
> > /Marko
> >
> > Philip Axer wrote:
> > >
> > >
> > > On Fri, 2009-11-06 at 10:11 +0100, Marko Isomaki wrote:
> > > > It works here using the same grlib version as you use.
> > >
> > > That's weird! I just tested it again on a clean/unmodified
> version. Same
> > > issue. RRobin => works, Fixed Priority => broken
> > >
> > > > Exactly what changes do you do to the unmodified grlib when
> > > > synthesizing the
> > > > system?
> > >
> > > Through the GUI I set:
> > > * Amount of cores to two
> > > * Round Robin off
> > > * FPGA type Virtex 4 LX100
> > >
> > > That's pretty much it.
> > >
> > > >
> > > > How do you observe the AMBA bus signals? If the default master
> setting
> > > > affects behavior it sounds like the AHBCTRL does not detect any
> active
> > > > bus requests at all.
> > >
> > > Currently, I have no logic analyzer available, thus I wired some
> signals
> > > to the user leds.
> > >
> > > The user manual states that hindex=0 has the lowest priority. Is that
> > > correct? Currently the boot prom is erased. Thus the core signals
> errorn
> > > and halts right after a reset. But that should be not an issue because
> > > the dbg uart has a higher prio anyways, right?
> > >
> > > Just for the record: I also checked the synthesis log, but I
> didn't find
> > > anything suspicious.
> > >
> > > I will be on vacation for the next weeks but I will continue to track
> > > down this issue once I'm back!
> > >
> > > Philip
> > >
> > > --
> > > Dipl.-Ing. Philip Axer
> > > Institut für Datentechnik und Kommunikationsnetze
> > > Hans-Sommer-Straße 66 38106 Braunschweig
> > > Tel +49 (531) 391 9662 Fax +49 (531) 391 4587
> > >
> > > [Non-text portions of this message have been removed]
> > >
> > >
> >
> >
>
>