This email group is for those interested in the LEON SPARC GPL'ed clone. Group Manager: leon_sparc-owner@egroups.com To subscribe, send a message to...
2
Dennis Rose
Dennis.Rose@...
Oct 21, 1999 4:58 pm
Jiri, it takes 23 minutes on an Ultra 10 to implement LEON-1 SPARC into an XCV300. That was at "fast implement" settings. We're running some experiments at...
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Dennis Rose
Dennis.Rose@...
Oct 21, 1999 4:59 pm
From Reto Stamm, here're the stats for the latest run of LEON-1.1 into XCV300: Fast (Low Effort): real 23:43.64 user 23:03.07 sys 6.72 Design...
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Dennis Rose
Dennis.Rose@...
Oct 21, 1999 11:25 pm
Here's a bit of info on PCI and on development board manufacturers for Virtex and Spartan parts. Xilinx PCI designs come with design files and support files...
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Dennis Rose
Dennis.Rose@...
Oct 22, 1999 2:04 pm
Guys, I looked at the pricing recently for XCV300-4BG352. Remember first these things: 1. FPGA prices drop 40% per year for the same part. 2. Quantity always...
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jgais@...
Nov 4, 1999 10:02 am
A cross-compiler (LEONCCS) for LEON is now available via the LEON home page at: http://www.estec.esa.nl/wsmwww/leon LEONCCSconsists of the following tools: GNU...
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Hans Tiggeler
H.Tiggeler@...
Nov 21, 1999 11:42 am
I wonder if anybody can answer a simple "AS to SIS" question. I am trying to write a simple assembler program, simulate it with SIS and then use it with Leon....
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Jiri Gaisler
jgais@...
Nov 21, 1999 9:26 pm
... You should use gcc directly. Consider the following code: .text .global start start: set 66, %g1 add %g1, 1, %g2 Assemble and link it with: sparc-rtems-gcc...
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Hans Tiggeler
H.Tiggeler@...
Nov 22, 1999 2:32 pm
Jiri, Thanks for your answer, it indeed solved the problem. I guess the real question I should have asked is if there is a sparc locator which takes an exe...
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jgais@...
Feb 18, 2000 2:51 am
This is to annouce the release of LEON-2.0, a synthesisable VHDL model of a SPARC V8 compatible processor. News: * Improved timing (45 MHz on Xilinx XCV300E-8)...
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Jiri Gaisler
jgais@...
Feb 19, 2000 1:10 pm
... As mentioned on the LEON home page, there is also a fault-tolerant version of LEON. This version is virtually SEU immune by design, including EDAC on...
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Jiri Gaisler
jgais@...
Feb 19, 2000 6:04 pm
... As mentioned in the LEON VHDL manual, the synopsys simulation and synthesis tools have too many bugs to correctly simulate and synthesise the standard...
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Dennis Rose
Dennis.Rose@...
Mar 7, 2000 6:16 pm
Jiri Gaisler received a very nice write up in eetimes.com's top story of 3/6/00! Take a look, it's a nice summary of what's been done. If you are actively...
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Hans Tiggeler
h.tiggeler@...
Mar 7, 2000 7:21 pm
Dennis, Indeed a good article although I am a bit surprise to read that you never actually downloaded the design to a Virtex :-) I belief that Jiri has the ...
15
Dennis Rose
Dennis.Rose@...
Mar 7, 2000 7:50 pm
Hans, Good info. At Xilinx we did the synthesis, mapping, place, route and timing analysis to get minimums back in October. Jiri modified the VHDL to infer...
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jgais@...
Mar 14, 2000 10:04 am
This is to let you know what is planned for the next release of the LEON model: 1. We are adding PCI interface "hooks" to allow to attach various PCI cores....
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Hans Tiggeler
h.tiggeler@...
Mar 14, 2000 4:48 pm
... mmm...., my TSC695E board is getting less and less attractive :-) ... Excellent idea, a boot loader is something you always need during initial...
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jgais@...
Mar 14, 2000 5:27 pm
... Don't worry, you can use Xilinx Virtex devices in space ... ... OK, but I intend to use the SelectRAM in the Virtex devices. Makes a dense and fast rom...
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Dennis Rose
Dennis.Rose@...
Mar 14, 2000 5:31 pm
I'm thinking it might be possible to boot LEON with a small monitor in internal Virtex E memory. Using the Chipscope ILA on-chip logic analyzer it would be...
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jgais@...
Mar 14, 2000 5:59 pm
... Thinking a bit further, since the selectRAMs can be initialised during programming of the device, I will add an option to boot from RAM rather than to...
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jgais@...
Mar 14, 2000 6:20 pm
Download statistics for the last three weeks: File downloads leon-2.0.tar.gz 814 leonspec.pdf 975 leonvhdl.pdf 891 The LEON...
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Michael Tzvetkov
michland@...
Mar 16, 2000 6:13 pm
... Yes, there is such problem. Has it been solved yet? Or i'll be first explorer? ;)...
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jgais@...
Mar 16, 2000 6:23 pm
... I don't use FPGA_express so I don't know how it infers rams. I guess the manual should tell you how... Regards, Jiri. ... Jiri Gaisler, ESA/ESTEC, Box 299,...
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Michael Tzvetkov
michland@...
Mar 16, 2000 6:27 pm
Have anybody simulated Leon model using Active-VHDL3.6? I've adopted tbench for AVHDL, but i've got crash during register file test phase. It looks like...
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Eric Smith
john_eric_smith@...
Mar 17, 2000 3:20 am
Hello Jiri, This may sound blasphemous but are there any plans to create a Verilog version of LEON? Thanks, eric ... From: jgais@......
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Sushil Kumar Kataria
Sushil.Kumar.Kataria@...
Mar 17, 2000 7:53 am
Dear Manager, I would like to become a member of Leon group for embedded applications. -- With thanks Yours Sincerely S.K.Kataria ... Dr.S. K. Kataria...
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Hans Tiggeler
h.tiggeler@...
Mar 17, 2000 8:23 am
Eric, Yes that is blasphemous :-) I assume you know you can get an Sparc V8 in verilog from Sun (see ...
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jgais@...
Mar 17, 2000 8:42 am
... I hope this was a joke .. :-) On the serious side, I don't really see the need for a verilog version - what can you do with verilog which you can't do with...
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Eric Smith
john_eric_smith@...
Mar 17, 2000 1:47 pm
Hello Jiri, Sorry no joke. It is just that we do all of our development using Verilog. thanks, eric ... From: jgais@......
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J. Hsu
jchsu88@...
Mar 19, 2000 6:46 am
Hi Jiri: I am new to this free Leon project. I am glad that someone finally do something that can break us from the domination of big corporation on processor ...
