Hi everybody! I am using snapgear 2.6-p42 to load linux 2.6.21.1 on my Leon3. My board is a ml509 (Xilinx). I want to connect Linux with an FSM via GPIO (FSM...
Hi, I am trying to add a module to grlib. I am using following values of the plug and play information for this module. haddr : integer := 10; hmask :...
Hi All, ... Speed Grade: -2 Minimum period: 9.814ns (Maximum Frequency: 101.892MHz) Minimum input arrival time before clock: 8.026ns Maximum output required...
Hi Jiri and everybody, To use the eCos together with the Leon3, I'm using the following tools available at Aeroflex Gaisler website: sparc-elf-4.4.2 ...
Hi All ! I have tried to synthesize Leon3 on Xilinx-ml510.. The design got synthesized successfully. ... ERROR:ConstraintSystem:59 - Constraint <NET "pciclk" ...
Hi all, can you explain why DSU is needed in asic design to simulate RTL? In make xconfig I deactivated both JTAG boundary scan and DSU but simulation in...
Hi, In my system configuration there are two AHB buses and processor cores on both the buses. these two buses have only a SRAM in common. (Say, one bus is less...
Hello, I am working with TSIM2 for LEON3. I want to use gcov to make sure my tests are effective. I have compiled my project with the options -ftest-coverage...
Hello everybody, I decided to use the command-module of GRMON to program flash memories of the board GR-CPCI-AT697 (memories recognized by GRMON as MT28F640J3)...
hi everyone i have interfaced an IP core in the SRAM area upper 512 MB for ramsn(4) by changing the mask .in simulation i am able to see transaction getting...
Hi, We are using board de2-115 and linux 3.3 (with all patches released). All steps to configure both interfaces have been followed and tested. Our problem is...
Hi, Assume that I develop a DMA engine to move data from the DDR to the AHB-RAM, does this affect the cache coherency in the multi-core gaisler system...
Hi, Xilinx map always crashs when I try to build the reference design for the leon3-gr-pci-xc5v. I use grlib-gpl-1.1.0-b4108. I tried it with ISE Release 12.4...
Can someone please explain me how to use the hcache signal properly? I have a simple AHB slave with a few memory mapped registers, but the cacheability of the...
The sram test module works incorrect if the number of data bytes in S-record file is not equal to 16. For example, the line (generated by srec_cat -generate...
Hello leon_sparc, I still using Greth API from grlib example. I want to Receive packet from eth0, then send it to eth1. Just passing it through. Using the...
Can anybody explain me why rtems gcc compiler doesn't compile a simple C source code with main? I need to adopt a rtems structured code to compile it... How...
Hello, Did anyone tried to connect the greth/grethm(have MII oder RMI interface as standard) with a Serial Gigabit Media Independent Interface to a Ethernet...
Hi, Finally I could run the LEON on Altera Stratix IV on DE4 Board (by terasic) and make use of GRMON to debug the cpu. I have some printf commands in my code....
Hey, Is it possible to define cacheability in a fine-grained fashion in a Leon 3 based system? The CACHED generic parameter isn't enough, because I can only...
Hi all, I have got a question on context switching. I noticed that a few RTOS would let users use this option: save minimum context (during thread switching or...
I've been trying to create a ahb to plb bridge and was looking for some simulation files for the AHB bus portion of things. I was looking around on the web and...
Hi! I'am wondering about the reason behind having icc registers at the execution stage (r.e.icc) As far as I have noticed and if I am not mistaken, these...
Hi, Now, in my system, I use a local instruction ram instead of the on-chip rom, with reset address is 0x00000000. I placed my program into the local instruct...
Hi Gaisler team, I once develop a busmatrix and integrate it in the grlib. Through simulation the plug&play can be detected " # ** Note: Stratix PLL locked to...
