Thanks Jiri for your reply I have another question, In the TSO model, a load by the IU checks its store buffer before going eventually to the external memory ...
Dear Jiri, I have 5 sram on my board which are 512k*36, can you suggest me a efficent way of mapping this sram to leon. Each sram had indivisual Control,...
It is not necessary to check the store buffer to insure the TSO model. Either the load returns with a cache hit and then automatically contains the latest...
Simplest thing is to use only one 512x36 sram. Connecting multiple will require to implement decoding and multiplexing of data read buses in the memory...
Dear Jiri, I have already connected one SRAM and it is working fine, But now I would like to connect other four, an you kindly give me some guidance. Thanking...
You one ram chip select per bank, and duplicate the address and control signals. The data bus must also be duplicated, but you need to add multiplexers on the...
... If the first instruction received the write error trap, then it should report "(trapped, tt = 0x2b)". But as you can see from the code I have copy-pasted,...
The write error trap is of the type "non-resumable machine-check exception", refered to in setcion 7.1 of the SPARC standard. Section 7.6 also refers to the...
Let me tell you the whole story. For some time now, we have been implementing our own SPARC MMU for LEON2-1.0.12. Our aim was to modify only LEON's structure...
Hi there, Happy New Year!! I am usig leon2-1.0.13(Standard edition). Is it possible to interface simultaneously both the Co-processor and the FPU to leon? Is...
Your concept can work, but you should only use mexc, not werr. A page miss should cause trap 0x09 if you have an mmu with hardware table walk, or 0x2c if you...
Thank you very much for the reply Jiri, I will try the method you suggested. Thank you once again. Happy new Year Sree Jiri Gaisler <jiri@...> wrote: ...
Hi , Please give me some pointers where to look for more documentation about meiko fpu and the data sheet of Meiko as well. Thanks in advacnce, Roohi...
I followed your guidelines and made some changes to dcache and iu, that seem to be successful. However, having to wait each time for the TLB check to be...
Right. That is why the MMU normally is integrated with the caches. A TLB search is really only necessary on a write miss, since a write hit can (should) not...
Hello I need to know the protocol of writing/reading in the cache memory for example: a single store takes 2 cycles. does the data_in have to be valid only ...
Hi, strange_steve, have u find out why the dpram_synp_ss : missing. I am facing the same problem now. please let me know. thanks regards, Keng ... to ... ...
Hi all Could anybody tell ahb arbiter working as per ahbarb.vhd Thank you __________________________________ Do you Yahoo!? Yahoo! Hotjobs: Enter the "Signing...
Hi Jiri, I'm testing performance of Leon in a AX1000-FBGA676 from Actel. Now I have a few questions about cache configuration in Leon. 1) What cache...
... 1 + 1 kbyte direct mapped. ... Which synthesis tool (and version) did you use? Also, make sure you use 'make xconfig' to configure the vhdl model, rather...
Thank you Jiri for your fast reply. I'm using Synplify for Actel version 7.3. And I am using 'make xconfig' to edit the configuration. The caches are 1 set, 1 ...
leon-xst work well with both synplify and Xilinx XST, and is the prefered distribution. leon-std is kept to keep compatibility with leon2-ft, but is no longer...
... After some further testing, I have found out that the current AX ports only supports cache sizes of 2 Kbyte and larger. You should thus configure the...
Hi I am a beginner. For me, i am using Xilinx ISE Webpack 6.1.03i with MicroSim XE II 5.7C. I tried to open the ..\leon2\leon2-1.0.21- xst\syn\xst\leon.npl. At...
Hey, first of all, I wish everybody a happy new year 2004. Now my problem. I have a simple program that works already from RAM. So I download it via dsumon and...
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