hello eduardo, ... hey, we have exactly the same board here, leon runs on it for some weeks now, but we didn't sent any patches for leon yet. i guess you won...
Hello Thanks for ur reply. But still i get this error.Checking expanded design ... ... 'mmu_cache' could ... edif or ngc ... not supported ... i checked my...
hi, I added a new output signal "led_on" to leon. The signal is attached to my LED. Now I am trying to turn on my LED through DSUMON. My program is supposed to...
Dear all, i am still having problem with printf instruction. I'm checking the value of the uart registers, uart 1 and 2 control registers. I have tried with...
Run the program once, and check if the LB and FL flags are still set after the program has terminated. If not, you must upgrade leccs to a later version,...
Thanks for having answered, FL and LB are still set after the program has terminated, as it can be seen by the following 0x80000078 UART 1 control register ...
Try to connect ddd/gdb through dsumon, and see if you can debug you program. You could also try to use the latest version of grmon instead of dsumon. Note that...
Hi, Pls help me with the solution to problem that I am facing, as mentioned below. when I am trying to run testbench in Modelsim Altera version, A warning is...
You have configured the model to use Xilinx specific clock generators. Set targetclk => gen in device.vhd or run 'make xconfig dep' and disable tech-specific...
hi, Thanks for mail. That did not solve the problem. I individually checked devices in device.vhd, I found that the WARNING " WARNING: Design size of 343...
Your version of modelsim is limited with the number of entities. Removing the mmu lowered the entity count and the simulation succeeded. Jiri. ... -- ... ...
I'm attempting to write to the PIO in 32 bit mode and have been unsuccessful. In my HDL I'm porting out datao(8) and probing it with a scope but nothing's...
Can anyone confirm that if the chosen Fpga technology only supports fully synchronous dpram (used for LEON2 register file) this particular block of Leon2 is...
Yes, the read port of the dpram used for the register file will be clocked on the negative edge. In fpgas, it is not a big problem since the embedded rams are...
hi, when i change mcfg1 it stays unchanged until i execute a program. dsu> mcfg1 0x00080033 mcfg1 = 0x00080033 dsu> leon 0x80000000 Memory configuration...
Yes, this is normal (see the manual). use wmem 0x80000000 <value> to change the mcfg1 value immediately. Jiri. ... -- ... Gaisler Research, 1:a Långgatan 19,...
hi, I attached pio[10] to a LED on my board. When I define my I/O Port in bit 10 as output, the bit in I/O register is set to '0' automatically. It changes...
Hi, I have downloaded the latest version of leon, uncompresed it, configured it(changed only to make target generic),I have done make dep, make vsim. Then when...
I added a APB slave module.I added the input signals(mydatain(15 downto 0)) in the leon.vhd. mydatain_pads: for i in 0 to 15 generate mydatain_pad: inpad port...
Hello Whenever i enable mmu in the Leon Configrution, i get this error when implementing the design. Without this i do not have problem. I use ISE 6.1. Virtex...
The MMU cannot be synthesised by XST, because the tool has bugs. Use synplify instead. Jiri. ... -- ... Gaisler Research, Första Långgatan 19 S-413 27...
This is a known bug in modelsim, upgrade to a later version (5.8) . Jiri. ... -- ... Gaisler Research, Första Långgatan 19 S-413 27 Göteborg +46-317758650 ...
Hello all, When I try to get my micron MT48LC4M32B2 SDRAM work on my Altera Cyclone board, I found that the dsumon detects wrong sdram :-(. I've enabled...
Hello, look at my previous mail how I implemented the vhdl to split the data/address lines: http://groups.yahoo.com/group/leon_sparc/message/4837 If this isn't...
After doing 'load hello', also do a 'veri hello' to verify that the program has been correctly downloaded. If veri fails, you have some hardware problems. ...
Hi I'm trying to run RTEMS applications using gdb that is connected to grmon and the grmon communicates with the DSU in LEON2. I have no problem connecting and...
Hello Tom, Yes I tried to link the buses like you do, but the same result, my synthesis tool is QuartusII 4.0, which should be OK... I really wonder why dsumon...
Jiri, I've done that and the result is error everywhere. i.e. from the first bit to the last. I believe dsumon didn't find my real sdram at all...but what is...
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