I try leon on GR-PCI-XC2V FPGA Development board and it's back board (with uarta and uartb),I link a linux pc to the dev board and through uar0(1) to another...
The RTEMS devices names for the LEON uarts are: UART1 = /dev/console UART2 = /dev/console_b The stdin/stdout are automatically mapped on UART1. To read or...
Hi all. I'm working from a unniversity job. I will study about uClinux's architecture for a port. I would like to ask something easy. Is there any paper,...
Pablo Silva
magoguevarapablo@...
Nov 2, 2005 2:35 pm
7525
This bug has now been resolved by Synplicity. To receive an update for your synplify software, contact Synplicity and refer to bug ID#00161255. Jiri. ... the ...
Hi Jiri, The simulation of the ahbtrace modules doesn't work, because the aindex register value is not initalized. Adding v.aindex:=(Others=>'0'); in the reset...
David.Krutz@...
Nov 2, 2005 8:37 pm
7527
The aindex register must be written by software before tracing can start, it is not reset on power-on. Jiri....
The dma.vhd is a very simple example of a AHB DMA engine. There is no documentation, but the code is simple... The register layout can be derived from the...
Hi ! i am tring to make the twothreads.c sample program from eCos run on 2 processors. I am simulating with Modelsim and I only get dissasembly output from...
I want to see contents of regfiles (contents of global registers, % g1,...%g7) and control registers (psr, wim, etc) when running testbench (tb_func32_disas)....
Hi, I followed the instruction on www.gaisler.com called "Linux for LEON processors". I run make xconfig and tried to set the settings from the screenshot on...
Sorry, I am simulating the LEON2 processor, so could you tell me the implementation of those registers in case of the LEON2 processor? thanks ... registers...
Hi Jiri I've a problem with the sparc-elf-gdb tool. I'm using the BCC-1.0.16-win32-mingw-toolchain. The gdb starts fine. When I try to open a remote-connection...
Hi All When I simulate leon3mp using ncsim (version 5.4-s008) , I got wrong simuation results compared to the results of modelsim. Are there anyone who using...
hi , I try use xilinx ise 7.1i to synthesize the "leon3mp " design. I use cygwin to change "leon3mp" directory then type "make xgrlib" command, and then...
You boot code must enable the remaining processors before jumping to ram. Uncomment the following lines in prom.S, and rebuild the prom code with 'make soft' :...
You need to configure the processor for virtex2 target technology. Run make xconfig and select virtex2 under 'Synthesis'. Exit with 'save and exit' and re-run...
Hi Jiri, of course I started TSIM with "-gdb". It waited for a connection on the port. What do you mean with "able to open the port"? Should I receive an...
Markus Danninger wrote: TSIM just sayd "gdb interface: using port 1234" This means that the port was open OK. Maybe you can try with 127.0.0.1:1234 instead of...
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