You SDRAM has 10 column bits, so the controller will support this SDRAM without problems. Note that the SDRAM controller can interface 64-bit SDRAM even when...
Hi all! I've build minimalistic leon3 based system (for VFX12) and wish run a eCos application on it (something like timeslice.exe from ecos-bsp-1.0). the...
Hi Jiri: We have found 1 bugs in bare-c tarball(sparc-elf-3.4.4-1.0.22.tar.gz). Please check it! sparc-elf-3.4.4/src/examples/Makefile line74 "mkinstalldirs ...
Hi Jiri: We have found 1 bugs in bare-c tarball(sparc-elf-3.4.4-1.0.22.tar.gz). Please check them! sparc-elf-3.4.4/src/examples/Makefile line74 "mkinstalldirs ...
Hello everyone, I found some funny diffence between sparc-rtems-xxx (version 4.6) and sparc-elf-xxx : I have a sipmle Hello-world-style progrma: it reads a...
Must be it beacause I use no rtems-specific defines: is it necessary? I thought i could the compiler without necessarly using rtems-specific features, my...
I would like to thank you for your last help "adding application to snapgear linux". Thanks Konrad -- _______________________________________________ Check out...
Hello, I have a problem with flash. Anyone help me I have the pci-xc2v board dsu> flash ... Dev 1: D[31..16] Dev 0: D[15..00] ... Manuf. Unknown Manuf.!...
Thank you very much Jiri, Richard and Konrad for your answers. Unfortunately I still have not managed to have the GR-XC3S boot SnapGear linux from PROM. This...
I installed the grlib 1.0.7 version and compiled and transferred the can_send_basic.c program provided. I still do not see any output across Pin 2 & 6 (or 7 &...
... Not quite. You should be able to enable the CAN and synthesise the design, but it is not necessary to modify the UCF file. If you look at lines 442-445 and...
Hi Jiri, Konrad and all I try to load a small video sequence in my SDRAM to apply a video treatment to him. I dont know if i must load this sequence like file...
Richard, Thank you for your time. I uncommented "g1" and "g2" and synthesized the .bit file again. I installed jumpers JP3 and JP5 at 1-2. The output across...
Ashwin, I see that you are trying to run some executable from the can_tb directory in grlib. Please note that these files can not be run separately, i.e....
... Can you please send me the file: grlib-eval-1.0.6\designs\leon3-gr-xc3s-1500\leon3mp.par grlib-eval-1.0.6\designs\leon3-gr-xc3s-1500\leon3mp_pad.txt so...
Hi manu92370 ... Firstly, what configuration or bit-file have you loaded into the FPGA? Is it one of the demo configurations which are on the CD with the...
I load board/gr-pci-xc2V/leon_xst.bit in the cd I use grmon-eval 1.0.10 when i do info sys, i obtained: grlib> info sys 00.04:00f European Space Agency...
... The GR-PCI-XC2V board is designed with 32 bit wide Flash prom, but GRMON indicates that 8 bit prom is detected. Therefore GRMON cannot correctly read the...
... Try the switches the other way round. open => '1' due to the pull-up resistor closed => '0' since the switch connects the pin to DGND. Does this work now?...
thanks very much I have a 32 bit prom I am apprentice, i must make a study about LEON. I have a another problem, i try to run hello application but i have ...
hello.During i added the grfpw.ngo to my project grlib-eval-1.0.6/designs/leon3mp,i met some problems. I configed the grfpu.And i copied the ngo into the...
i have some questions in the precess of synthesizing the leon3mp(grlib-eval-1.0.6 version) with Design Compiler (2001.08 version).i use the "analyse-elaborate"...
The grfpu netlist was loaded into your design by ngdbuild, and properly merged by the mapper. However, the place & route program (par) encoutered an internal ...
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