I have to use GENIO(0-11),GENIO(20-31) & GENIO(40-51). Looking at the GRIP user manual, I see the addess offset for the data, output and direction registers to...
Hi Jiri, all Thanks for the info on ddd/gdb. I now have "Hello world". I was using that to get the debugger working for the c-irq sample. Using the same route,...
Take a look at the code in c-irq.c. You need to define LEON3 to run it on a LEON3 system, otherwise it is compiled for LEON2. Compile with: sparc-elf-gcc...
Thanks for your reply. I'm sorry for asking what I see now that I could have found in the manual. Anyway, even with the -lsmall option, the executable weighs...
Did you try the -qsvt option? When I compile an empty program, the minimum foot-print is 5 Kbyte: jiri@amd64:~/examples$ sparc-elf-gcc -qsvt -msoft-float...
The file size has obviously nothing to do with the size of the binary, as it includes the symbol table and debugging information. The 5 Kbyte includes support...
Hello Jiri, Thank you very much for your support so far. In your new Bcc release for windows there is a folder called src. However under this folder i can not...
Hello Jiri, Thank you for your quick answer ! Because i must build my application as standalone. It means my ultimate binary should run independent from mkprom...
What is the base address for the GENIO? From an example Richard sent me, I know the PIO has a base address of 0x80000800 for the input register. Is this the...
Hi Ashwin, ... On the GR-XC3S1500 development board the GENIO signals are general purpose i/o signals to/from the FPGA to the 40 pin connectors on the board. ...
Thank you, Richard. I have a better picture now. I intend to use some of the GENIO pins for just I/O purposes. I don't know much about tweaking the VHDL ...
See message http://groups.yahoo.com/group/leon_sparc/message/8206 for some problems with the spirit flow,and why it is unsuitable for leon3/grlib at this time....
BCC compiler v-1.0.24 is now available for download: ftp://gaisler.com/gaisler.com/bcc/ Binaries for linux and cygwin are provided, as well as the latest...
Hi guys, I'm a new user thus I may ask some silly questions. There is only a Xilinx virtex-4 development board with me and I want to implement leon2 on it. But...
Hi Jiri, Thanks for linking to your previous SPIRIT post. It's good to know where you stand on SPIRIT. I agree that SPIRIT has a way to go, but think it's a...
... There are several ways you could implement it, and you would have to modify several files. I will think about it and try to suggest a simple way you could ...
I use the Xilinx ISE version 7.1.03i to compile and systhesize the leon2 on virtex4. After compiling the debug package, there comes an error: Error:...
Hi Jiri and all, Has any one tried adding the open cores FPU (from Jidan El-Iryani) to Leon ? Regards, Ankur Mehta....
Ankur Mehta
ankurm@...
May 5, 2006 5:03 am
8890
Hello Jiri and all, Sorry for insisting, but I still cannot connect to LEON3 DSU. I'm using the same user constraints file as in my previous LEON2 design. I'm...
Stéphane Davy
stephane.davy@...
May 5, 2006 7:10 am
8891
... It does not make much sense to interface the opencores FPU to leon, since the FPU lacks conversion and compare instructions. This means that you will still...
GRMON supports the Xilinx parallell cable III. You will need to check if the cables are identical. If not, then the Altera cable cannot be used. Jiri....
first of all, let me appologize for asking such a basic question, but as I am new in this field, I need to start somewhere. As for the question, I want to...
HI: Jiri and everybody! I'm trying to run 2 cpu cores in the system. I set the system as the following steps; 1.In grlib/designs/leon3mp/config.vhd,set the...
Having problems with message search?
Fill out this form to ensure your group is one of the first to be migrated to the new message search system.
