Hi Jiri and all, Ever since I tried to with ML402 board and do PAR myself and load it on the board, I failed to get into the debug mode. So this time, I...
I'm synthesizing Leon3 using Xilinx ISE 6.3 and I'm analyzing the reports to observe the characteristics of the processor. On the site www.gaisler.com at the...
I am using a union consisting of a 16bit raw value, and also a struct with the individual bits defined. When using bcc v3.2.3, this compiles OK, but when using...
It seems to me like the grmon JTAG interface does not work with your version of windows. I suggest that you use the serial port instead. Connect a null-modem...
Hi Jiri, Is it not possible, using grmon-eval, to set software breakpoints in Local Instruction Ram ? (0x8e.. ....) Whenever I set one, resuming CPU execution...
Hello Jiri and all, I recently programmed an Actel AX1000 with Leon3 inside. The DSU detection of the config works fine. There is a problem when trying to...
I think the solution must be to latch the MULTIPLEXER POSITION at falling edge of (low active) RAMSN (or any other memory access). And not the data. So that...
A soft breakpoint in grmon is currenly not possible. If you have enabled any watchpoints in the processor config, you can use hard beakpoints using the hbreak...
We have updated the Gaisler plugin for eclipse/CDT to support the lastest version of eclips (3.2.1) and Calisto. The benefit is that the 'break' button now...
Hi I did the synthesis of LEON Processor using the synopsis design compiler, and then I try to capture the switiching activity using the modelsim to calculate...
hi, In the leon user manual it says that "...It is not possible to enable snooping when an MMU is present in the system, since the cache addresses are virtual...
Yes, it is not currently possible to maintain cache coherency when the MMU enabled. The simplest way to solve this is to extend the cache tags with the...
Hi everyone, after dowloading a given leon configuration on a Xilinx board and then trying to use debug support unit through serial cable, the following ...
Hi Jiri, I simulate the RTL of the DMA engine of GRPCI core, programming it to read data from a 0 wait state simulated memory into an AHBRAM on-chip RAM. I set...
Hi Jiri and everyone, While I was trying to PAR on ML401 designs using grlib-gpl-1.0.10- b1800 (new grlib), I keep getting timing errors while I have no ...
Has anyone got Java runing on a LEON system? I would be especially interested in a GCJ [1] port for LEON. I want to compare compiled Java on a RISC with a Java...
Virtually tagged and virtual indexed. If you keep the cache set size 4 Kbyte or lower, the virtual and physical index would be the same since the MMU page size...
Hi Jiri, I hope you'll excuse me for I insist regarding my previous message (#9907). I'd really like to know if, in the present RTL design of <pci_mtf.vhd>, it...
The PCI fifo is used in ping-pong mode. Half of the fifo is first filled, and then emptied on the AHB bus while the second half is filled. To get shorter...
The flow work correctly unless you have modified the design. You can see the complete log file on our web site: http://gaisler.com/doc/make_ise_ml401.txt ... ...
A graphical version of grmon is now available. Based on the eclipse rich-client platform, GRMON-RCP provides a graphical interface to all GRMON functions. And ...
Thanks for the quick reply. I wonder now if we extend the L1 cache to 32KB and add a 32MB L2 cache physically indexed and physically tagged, then when the L2...
hello everybody I am working on design of fault tolerant features of leon2 processor memory management unit. i need some clarifications Instruction cache is...
Hello Jiri and all, I programmed a new Actel AX1000, with internal peripherals muxed with external SRAM, and Leon3 now detects my 1MB of SRAM. When I load and...
I think you are seing a data trap (tt = 0x9) caused by AHB error. Have you enabled I/O access in mcfg1 of the memory controller? Otherwise you cannot access...
Yes, I enable it in the program: MCFG1_pt = (int*)0x80000000; *MCFG1_pt |= 0x10080000; //0x10080000: 32 bit wide, enabled, no wait state but when I check...
... Running No, researching yes, excited about the possibilities.. definetely. Muvium is an Ahead Of Time Java compiler that specifically targets very small...
You must use volatile pointers when declaring register pointers, or the assignments can be removed by the compiler: volatile int *MCFG1_pt = (volatile int *)...
... sounds interesting. ... That's exactly what I was looking for - a JVM on the 'bare metal' as it is named sometimes. ... A rough proof of concept would be...
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