Hi, I'm planning to start using the LPC2888 (especially because of the USB HI speed), I couldn't find any development board for it, do you have one to ...
... I checked out the latest NXP Boot Loader 1.66 on upgrading my LPC2292. Although not documented in the description, the R and other related commands that...
Development borad: Try Nohau LPC2800 board. Infact they are the only one who currently have working reference design for LPC2888. We have used this and has...
I'd like to resurrect this thread. We've experienced a very similar-sounding problem. We were getting data abort exceptions on the same processor, in interrupt...
Bryce, try disabling the MAM. I believe one of the changes being made in the silicon revision NXP are currently doing is to fix the MAM. I changed my...
... made in the silicon revision NXP are currently doing is to fix the MAM. I changed my application to leave the MAM disabled after seeing similar issues...
... seeing ... there ... ...and if you check the errata for the device there's a documented problem with the PLL (max Fcco is 290 Mhz rather than 550 Mhz). ...
Is it possible to run the RTC from vBatt while Vdd is sitting at 0V? There seem to be mixed opinions of this on the forum and the data sheet is anything but...
Hi, You can run the LPC2138 RTC from Vbatt with Vdd = 0volts. The only draw back I see is the size off battery to keep the RTC alive for a long period of time...
... Hi Bryce, Are you able to say more what you mean by "complex IRQ and FIQ interrupt handers"? What about DMA? If the CPU or PLL clock speed limit is not...
I too am trying to work out if this is possible encoder/decoder chips such as TIR1000 from TI require a clock 16X the baud rate, the lpc2138 user manual...
Hi, I'd like to reset my LPC2194 on demand by code, when a certain condition is met. How can I get this? Have to to a branch o address 0 or something like ...
... Hi, it is possible to do directly from C using this construct: #define BOOT_ADDR 0x0000 ((void(*)())(BOOT_ADDR))(); Personally I prefer forcing an...
Hi Carlo, thanx for your quick answer. Probably you are right, it's far better to do a HW reset using the watchdog. I'll never manage, I hope it's easy,...
Sorry if I'm disturbing you again, Carlo. Do you think this code is feasible to get a HW reset with the watchdog? WDTC = 0xFF; WDMOD = 0x03; WDFEED = 0xAA; ...
... We're not using DMA, just non-trivial code executing comms protocols, etc. ... We've triple-checked the PLL and our interrupt stubs. They are not ...
... protocols, etc. ... case, I ... are ... Two questions: - what are your PLL control register settings (and i/p clock frequency)? - is the code you posted...
... Our input clock is an external 32768 Hz watch crystal, with a PLLCFG value of 0x12254, yielding a PLL frequency of 287965184 Hz. ... Yes, it is a function...
... These value look OK (though by my calculation it's 287,965,183 Hz). ... And FIQs - presumably they're enabled while this is happening? What sort of context...
... As I've previously said, I already have a workaround that works for me. For now, we're lowering the MAMCR to 1. I'm not really interested in other...
... Yes ... FIQ_Handler: ldr r9, =start_nop ldr r10, [r8, #+8] /* r10 = initial T0TC */ cmp r10, #32 /* T0TC should have been reset to Zero on the FIQ...
... I can see your point, but it were me I'd want to get to the bottom of it. You have a system that's failing, cause unknown. As far as you know, you're using...
I'll try to explain my scenario as best as I can. I am using the LPC2103 and am trying to implement a system which reads in pulses from an optical encoder, I...
... I don't think that you need "multi threading". You will need to shift your point of view when devising an embeded program though. When writing an...
Are you using the RTC interrupt? And if you are are you keeping tack of the second count inside the interrupt?? are you clearing the RTC interrupt?? Thanks ...
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