Would there be some way to bring this to 222 MHz? I believe we have
100 KHz data channels allocated there (in this region) that have never
been used.

Bill - WA7NWP

On Sat, Jun 27, 2009 at 11:08 PM, John Champa<radioskyart@...> wrote:
>
>
> *Hello!*
> **
> *Comments and suggestions for further experiments, please? John is looking
> for some other*
> *stations to help with the experiements. Post your comments here and / or to
> John KD6OZH directly.*
> **
> *Thanks,*
> *John K8OCL*
>
> ---------- Forwarded message ----------
> From: John B. Stephensen <kd6ozh@...>
> Date: Thu, Jun 25, 2009 at 7:32 AM
> Subject: OFDM Activity
> To: k8ocl@...
>
> Hi John,
>
> I haven't done anything on 6 meters since the STA expired. I've been making
> a less expensive version of the DCP-1 hardware that is more flexible. The
> external microcontroller has been replaced by a soft CPU inside the FPGA.
> The winter TAPR newsletter has an article on this CPU and the source code is
> on the TAPR web site. I've ported all of the Verilog code developed during
> HSMM working group era to the new FPGA and a later version of the Xilinx
> develoment tools. The modules that were tied together in hardware are now
> peripherals for the soft CPU and several more have been added to support
> traditional analog modes. I've attached a block diagram and some pictures of
> the new PCBs. I plan to pulish more on the PCB and the rest of the Verilog
> and assembly language code as testing progresses.
>
> This new board can generate and process 1-30 MHz RF directly. I'm now
> testing soft CPU code for the various modes and have SSB and ISB
> transmission and reception working plus FM and OFDM transmission. I should
> have FM and OFDM reception working soon. The soft CPU scheme allows the
> DCP-3 hardware to be easily switched between analog and digital modes so it
> can be used to build a general-purpose radio or fed into a transverter. The
> final configuration is intended to be a device that will switch between
> analog voice and TCP/IP data via the ethernet port.
>
> I plan to do more on-the-air testing this summer. The new Verilog tuner and
> modem modules can handle signal bandwidths between 1.6 MHz and 500 Hz, so
> I'm no longer restricted to VHF and UHF. I may do initial testing on 80
> meters with 6 kHz wide OFDM that could support 9.6 kbps under good
> conditions. Anything that will work on HF will work even better on VHF and
> UHF frequencies. Switching to 750 kHz wide 1.2 Mbps signals is now a matter
> of loading new filter coefficients from flash memory.
>
> After testing on 80 m and 70 cm, I could apply for renewal of the STA for
> wideband 6-meter tests. However, it's probably more useful to find few other
> stations that could test on 80 m or 70 cm first. I had to use up 120 square
> inches of 4-layer PCB to get a prototype, so I made four DCP-3 PCBs and two
> other variations. One simple route to more widespread testing may be to
> produce a few adapters for transverters with 28 MHz IFs. I'll see what
> happens in the fall after I've done more on-air testing myself.
>
> Since the DCP-3 is easily programmable there is another alternative for the
> 6-meter bands that is currenlty legal and could be developed. OFDM is
> limited to AM voice bandwidth on the VHF bands. However, 8PSK could fit in
> the same 20 kHz bandwidth as 9600 bps FSK and could operate at 3 times the
> data rate. I did put AX.25 accelerator logic in the FPGA, but it will be a
> while before I have time to test it on anything but the logic simulator.
> It's intended be used to implement 9.6-76.8 kbps FSK modems for amateur
> satellites which is what originally got me interested in doing a DSP
> project.
>
> 73,
>
> John
> KD6OZH