The XIO / PCI chapter of the PNX17xx series databook
is a bit unclear on the upper 8 bits of the XIO bus.
The lower 8 bits are shared with the PCI bus, so they
are clearly tristated when the PNX17xx does not have
the bus. The upper 8 bits, normally used only for
XIO cycles are not part of the PCI bus. Are these
signals also tristated whenever the low 8 data bits
are tristated? Basically I need to know if I can
connect these together on multiple PNX17xx processors
on the same shared PCI bus?

Thanks for any assistance,
Gabor Szakacs