IEEE TTTC DELTA'04 - Call for Papers
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1. Announcement at a glance
Call for Paper for the IEEE International Workshop on
Electronic
Design, Test and Applications: (DELTA2004)
Burswood Resort, Perth, Australia, January 28-30, 2004
http://delta2004.ecu.edu.au/>http://Delta2004.ecu.edu.au.
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2. Important dates of the next weeks
15th, aug.: Camera ready for DFTS'03
15th, aug.: Camera ready for ATS'03
18th, aug.: Notification of acceptance for HLDVT'03
22th, aug.: Camera ready for Therminic'03
31th, aug.: Notification of acceptance for WRTLT'03
2nd, sep.: Submission deadline for TECS'03
5th, sep.: Camera ready for BTW'03
7th, sep.: Submission deadline for DATE'03
10th, sep.: Camera ready for IIP'03
11-12 sep.: ECS'03, Bratislava, Slovaquia
22-25 sep.: CSIT'03, Yerevan, Armenia
24-26 sep.: THERMINIC'03, Aix en Provence, France
28sep-03 oct.: ITC'03, Charlotte, USA
02-03 oct.: BTWQ3, Charlotte, USA
02-03 oct.: FATE'03, Charlotte, USA
02-03 oct.: I-IP'03, Charlotte, USA
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3. Full announcement
CALL FOR PAPER
IEEE International Workshop on Electronic Design,
Test and Applications (DELTA 2004)
January 28-30, 2004, Burswood Resort,
Perth, Australia
The main goal of DELTA 2004 is to bring together specialists from
all
over the world to meet and to discuss research and engineering
problems and results in the emerging area of electronic design,
manufacturing, test, advanced system applications and related
areas.
Scope: Original contributions are sought in the wide range of
the
areas of electronics design, test and applications including
(but are not limited to):
Design
Digital Devices, Components and Techniques
Analog Components and Techniques
System Architecture, Simulation and Modelling
Microprocessors and ASICs
MicroPhotonics, Opto-VLSI
Power Electronics
Multi-Chip Projects
Packaging, Practical Realisation & Field Trials
Emerging Technologies, Design & Re-Use
Testing
System Testing
Design Verifications
Built-In Self-test Techniques
Design for Testability, Boundary Scan
Analog and Mixed-Signal and RF Test
Fault-Tolerant and Robustness
Concurrent Checking and On-Line Testing
Measurement for Reliability and Safety
Assessment
Characterisation Testing, Performance Modelling
and
Analysis
Sequential Circuits Test and Memory Test
Applications
Communications and Networking
Signal Processing
Fuzzy Logic and Neural Networks
Instrumentation, Measurements and Control
Medical Electronics
Automotive, Security
Real-Time Systems
Novel Systems and Applications
Multimedia, Education, Technology Transfer
Special sessions: Proposals are sought for organising special
sessions and tutorials/seminars on hot topicsin design, test and
applications. Among the sessions of interest are
Advances in FPGA Based Design
MicroPhotonics System Design & Test
Mixed-Signal Testing
Industrial Experiences & Challenges
Tutorial: In conjunction with the workshop, two one-day
tutorials
will be held on January 27, 2004.
Submission of Abstracts: Prospective authors are invited to
submit
an extended abstract including:
Paper topic
1000 word paper summary
Affiliation and address of each author
The contact authors postal and e-mail address
A short biography of the principle author
Submissions should be made electronically as PDF (preferred) or
standard non-encapsulated Postscript files through the website
<http://delta2004.ecu.edu.au/>http://Delta2004.ecu.edu.au. In
submitting an abstract the authors agree that, upon acceptance,
they
will prepare the final manuscript in time for the inclusion into
the
formal IEEE Computer Society published proceedings, and will
present
the paper at the Workshop.Final manuscripts will not be
published
without advance registration.
Key Dates:
Submission August 22,
2003
Notification of Acceptance October 3,
2003
Submission of final manuscripts October 31,
2003
Organizing Committee
General Chair: Adam Osseiran, ECU, AU
Program Co-Chair: Serge Demidenko, Monash U, MY
Program Co-Chair: Michel Renovell, LIRMM, FR
Finance Chair: Marilyn Crosthwaite, ECU, AU
Local Arrangement co-Chair: Douglas Chai, ECU, AU
Local Arrangement co-Chair: Stefan Lachowicz, ECU, AU
Publication co-Chair: Kamal Alameh, ECU, AU
Publication co-Chair: A. Salim Bouzerdoum, ECU, AU
Publicity Chair: Wlodek Gornisiewicz, ECU, AU
Administration Officer: Pat McGinley, ECU, AU
Program Committee:
Vishwani.D. Agrawal, Rutgers U, USA
Maan M. Alkaisi, U of Canterbury, NZ
Anthony P. Ambler, U of Texas, USA
Michael L. Bushnell, Rutgers U, USA
Don Bouldin, U of Tennessee, USA
Srimat T. Chakradhar, NEC, USA
Trevor Cole, AMN, AU
Rolf Drechsler, U of Bremen, DE
Laurie Faraone, UWA, AU
Joan Figueras, UPC, SP
Ran Ginosar, Technion, IL
Patrick Girard, LIRMM, FR
Ad J. van de Goor, Delft U, NL
Dimitris Gizopoulos, U of Piraeus, GR
Barry Harrison, Griffith U, AU
Hiromi Hiraishi, Kyoto Sangyo U, JP
Michiko Inoue, Nara Inst of Tech, JP
Bashar A. Issa, U of UAE, UAE
Andre Ivanov, U of BC, CA
Marcel Jacomet, Biel Sch of Eng, CH
Seiji Kajihara, Kyushu Inst. of Tech., JP
Hans G. Kerkhoff, U of Twente, NL
Sandip Kundu, Intel, USA
Christian Landrault, LIRMM, FR
Chung-Len Lee, Nat. T-H U, TW
Mike Lee, Dongshin U, KR
Cheng Chew Lim, Adelaide U, AU
Fabrizio Lombardi, NE U, USA
Marcelo Lubaszewski, UFRGS, BR
Rafic Makki, U of NC at Charlotte, USA
Peter Maxwell, Agilent Technologies, USA
Chris Messom, Massey U, NZ
Alex Orailoglu, U of CA at SD, USA
Zebo Peng, Linkoping U, SE
Sudhakar M. Reddy, U of Iowa, USA
Jacob Savir, NJ Inst of Tech, USA
Donatella Sciuto, Poly of Milan, IT
Bayan Sharif, U of Newcastle, UK
Chauchin Su, N. Chiao Tung U, TW
Jack Singh, Victoria U, AU
Mani Soma, U of Washington, USA
Renato Stefanelli, Poly of Milan, IT
Prab Varma, Veritable Inc., USA
Mike Wong, Poly U, HK
Cheng-Wen Wu, Nat T-H U, TW
Thomas W. Williams, Synopsys, USA
Younggap Yu, Chungbuk U, KR
Yervant Zorian, Virage Logic, USA
Steering Committee
Serge Demidenko, Monash U, MY
Kamran Eshraghian, ECU, AU
Paolo Prinetto, Poy of Torino, IT
Michel Renovell, LIRMM, FR
Regards,
CP Ravikumar
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