Dear Colleagues,

We look forward to your participation in 18th International
Conference
on VLSI Design and 4th International Conference on Embedded Systems,
2005. The details are given below.

The deadline for advance registration is 30th November 2004. Please
see
instructions on the web
(http://www.isical.ac.in/~vlsi2005/registration.html) for
registration.

We look forward to seeing you at the Conference.

Best wishes,
Susanta Chakraborty
Publicity Chair

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VLSI Design 2005

The Eighteenth International Conference on VLSI Design
and
The Fourth International Conference on Embedded Systems Design

Theme: Power-Aware Design of VLSI Systems

January 3-7, 2005,
Hotel Taj Bengal, Kolkata, India

http://www.isical.ac.in/~vlsi2005/

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The 18th International Conference on VLSI Design will be held jointly
with the 4th International Conference on Embedded Systems Design in
Kolkata, India, during January 3-7, 2005. It will bring together
eminent

researchers, academicians, and engineers working in VLSI design and
embedded systems from all over the world. This is a leading and
prestigious international conference held annually in India, with a
very

strong technical program. It offers a unique opportunity to
participants

to meet researchers and practicing engineers in the areas of VLSI and
embedded systems from both within the country and abroad. The major
attractions of VLSI Design 2005 include Keynote & Plenary Speeches,
Banquet Lecture and Invited Lectures / Tutorial. These will be
delivered

during the conference by eminent speakers of international repute on
a
wide range of topics. The list of speakers includes Fellows of IEEE,
Fellows of ACM, Distinguished Lecturers of the IEEE EDS, CASS and
SSCS
societies, Distinguished Fellows from industry, and other eminent
experts in areas ranging from VLSI Design to Device Technology.

The VLSI Design conference is well known for its highly successful
series of tutorials. VLSI Design 2005 and ICES-4 will feature eight
tutorials on a wide variety of topics ranging from device technology
to
system design. The tutorials will be conducted by leading groups from
across the world both from industry and academia. The tutorials are
expected to be of great benefit to students, researchers, and
practicing

engineers working in the broad areas of VLSI design and embedded
systems.

A large number of research papers will be presented during the three
days of the conference with representation from industry, academia,
and
R & D organizations. VLSI Design 2005 and ICES-4 have attracted 352
papers of very high quality out of which 97 regular papers, 5
embedded
tutorials, 16 short papers, 25 poster papers have been accepted for
presentation at the conference. Selected Design contest entries will
also be presented.

An Industry Forum is also being organized as a part of VLSI Design
2005
and ICES-4 where finished designs from industry participants will be
discussed, offering a great opportunity for industries to interact
with
each other and exhibit their achievements. Exhibit stalls and
presentations from various industries will further enhance
interaction
with industry participants. A special Research Scholars forum is also
being organized where research scholars will get an opportunity to
display their work through Posters and obtain valuable feedback from
the

conference participants.

The VLSI TRUST 2005 under the auspices of the VLSI Society of India
(VSI

- http://vlsi-india.net/vsi/) and Indian Statistical Institute,
Kolkata,

is organizing VLSI Design 2005 and ICES-4. The conference is held
with
technical co-sponsorship from IEEE Electron Devices Society (EDS) and
IEEE Circuits and Systems Society (CASS), IEEE Solid-State Circuits
Society (SSCS) and in cooperation with Special Interest Group in
Design
Automation (SIGDA), ACM.

RESEARCH PAPERS in the following areas will be presented:

DESIGN METHODS TRACK
· Process technology
· Processor design
· Analog-digital mixed signal SoC
· Concurrent package and board design
· CMOS and interconnect reliability
· Integrated circuit manufacturing
· Device modeling and simulation
· Signal integrity and circuit marginality issues
· Low-power design
· DSP design
· Functional verification

DESIGN TOOLS TRACK
· High-level synthesis
· Logic synthesis
· Design validation
· ASIC design
· Core-based systems
· Test and DFT
· Analog CAD
· MEMS
· Performance-driven design
· Physical design
· Programmable devices
· Standards
· Digital imaging
· SoC design platforms

EMBEDDED SYSTEMS TRACK
· Hardware/software co-design and verification
· Embedded software design
· Reconfigurable hardware design
· Architecture mapping
· FPGA-based design

List of Keynote Speakers:
- Prof. C. L. Liu, National Tsing Hua University, Tiwan
- Dr. Shekhar Borkar, Intel Corporation
- Dr. Alan Naumann, CoWare
- Dr. Ted Vucurevich, Cadence

Banquet Speaker:
- Dr. Wally Rhines, Mentor Graphics

Plenary Speakers:
- Dr. J. Bergeron, Synopsys
- Dr. Y. Zorian, Virage Logic
- Dr. R. Sentinathan, ATI

Tutorials: January 6-7, 2005.

T1 : Power-Aware reliable microprocessor design (Invited Tutorial)
Presenter: Pradip Bose, IBM T. J. Watson Research Center

T2: Title: High-Speed Interconnect Technology: On-Chip and Off-Chip
Presenters: Ramesh Harjani, Jaijeet Roychowdhury and Sachin S.
Sapatnekar, Department of Electrical & Computer Engineering,
University
of Minnesota

T3A: (Half day)
Title: Testing Nanometer Integrated Circuits: Myths, Reality and the
Road Ahead
Presenters: Shawn Blanton, Carnegie Mellon University, Subhasish
Mitra,
Intel Corporation & Stanford University.

T3B: (Half day)
Title: Test Methodologies in the Deep Submicron Era - Digital, Analog
and RF
Presenters: A. Chatterjee, Georgia Institute of Technology,
A.Keshavarzi, Intel Corp, A. Patra and S. Mukhopadhyay, IIT Kharagpur

T4: (Full day)
Title: SoC Design Methodology: A Practical Approach
Presenters:
Atul Jain, Texas Instruments Inc, Dallas,
Anindya Saha, Texas Instruments Inc, Bangalore,
Jagdish Rao, Texas Instruments Inc., Bangalore.

T5: (Full day)
Title: Good, Cheap, and Fast Testing of Digital Monster Chips
Presenters:
Bram Kruseman - Philips Research Labs, Eindhoven, The Netherlands
Sybille Hellebrand - University of Innsbruck, Innsbruck, Austria
Erik Jan Marinissen - Philips Research Labs, Eindhoven, The
Netherlands

T6: (Full day)
Title: Recent Advances in Verification, Equivalence Checking &
SAT-Solvers
Presenters:
Dhiraj Pradhan, University of Bristol
Magdy Abadir, Motorola
Rolf Drechsler, University of Bremen, Germany
Kerstin Eder, University of Bristol, UK

T7A: (Half day)
Title: Compact MOSFET Models for Low Power Analog CMOS Design.
Presenter: A. B. Bhattacharyya, Jaypee Institute of Information
Technology

T7B: (Half day)
Title: Physics and Technology: Towards Low-Power DSM Design
Presenters: D. Mukhopadhyay, Jadavpur University, P. K. Basu,
Institute
of Radiophysics and Electronics, University of Calcutta
V. Ramgopal Rao, Indian Institute of Technology, Bombay

T8: (Full day)
Title: Architectural, System Level and Protocol Level Techniques for
Power Optimization for Networked Embedded Systems
Presenters:
Luca Benini, Universita De Bologna, Italy
Sandeep Shukla, Virginia Tech, USA
Rajesh Gupta, University of California at San Diego, US


FELLOWSHIPS

The Steering Committee will award fellowships, based on need and
merit,
to partially cover expenses of students and faculty members from
India.
Applications must be submitted by October 15, 2004, using the
conference

website.

IMPORTANT DATES

Camera-ready papers : October 8, 2004
Camera-ready Design Contest entry submission : October 8, 2004
Fellowship application submission : October 15, 2004
Advance Registration deadline : November 30, 2004
Conference dates : Jan 3-5, 2005
Tutorial dates : Jan 6-7, 2005
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SPONSORS

Gold Sponsors
Cadence
Intel
Mentor Graphics
Synopsys
Texas Instruments

Silver Sponsors
Centillium
CoWare
Infineon
National Semiconductor

Bronze Sponsors
Virage Logic

Sponsors & Exhibitors
CG-Corel
IBM
Interra
Logic Vision
nSys
Techno
Trident
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Conference Event Manager: New Wave Display Services Pvt. Ltd.

For more information, visit http://www.isical.ac.in/~vlsi2005/

E-mail contact

For registration related queries please write
to:vlsi05regn@...
For any other query please write to the
organizers:vlsi05org@...

The registration fee table is included here for convenience
(Please visit the web site for instructions to register)


*Registration Fee (FOR DELEGATES FROM INDIA)

Members: Amount (INR)

Conference (Jan. 3-5) :

* Up to Nov 30 ------ 5500 [ ]
* From Dec 1 ------- 6500 [ ]

Tutorials(Jan. 6 - 7)

1 day

* Up to Nov 30 ------ 2000 [ ]
* From Dec 1 ------- 2500 [ ]

2 days

* Up to Nov 30 ------ 3500 [ ]
* From Dec 1 ------- 4500 [ ]

Non-Members: Amount (INR)

Conference (Jan. 3-5) :

* Up to Nov 30 ------ 7000 [ ]
* From Dec 1 ------- 8000 [ ]

Tutorials(Jan. 6 - 7)

1 day

* Up to Nov 30 ------ 2500 [ ]
* From Dec 1 ------- 3000 [ ]

2 days

* Up to Nov 30 ------ 4500 [ ]
* From Dec 1 ------- 5500 [ ]



*Registration Fee (FOR DELEGATES FROM ABROAD)

Members: Amount (USD)

Conference (Jan. 3-5) :

* Up to Nov 30 ------ $145 [ ]
* From Dec 1 ------- $175 [ ]

Tutorials(Jan. 6 - 7)

1 day

* Up to Nov 30 ------ $70 [ ]
* From Dec 1 ------- $85 [ ]

2 days

* Up to Nov 30 ------ $120 [ ]
* From Dec 1 ------- $145 [ ]

Non-Members: Amount (USD)

Conference (Jan. 3-5) :

* Up to Nov 30 ------ $180 [ ]
* From Dec 1 ------- $220 [ ]

Tutorials(Jan. 6 - 7)

1 day

* Up to Nov 30 ------ $90 [ ]
* From Dec 1 ------- $110 [ ]

2 days

* Up to Nov 30 ------ $150 [ ]
* From Dec 1 ------- $180 [ ]




Notes:
· Last date for Advance Registration is November 30, 2004
· For Day 1 and 2 of the Tutorials, please see the detailed technical
program.
· The conference fee includes the registration kit, CD-ROM containing
proceedings of this conference and archives of past years, lunch,
coffee

service, high-tea and banquet dinner.
· Tutorial fee includes tutorial material, lunch, and coffee service.
· For a hard copy of the Conference Proceedings, add US $ 100 (Rs.
4000/-)

Members: Members of IEEE, ACM, VSI

Special negotiated rates for hotel accommodation are available at the
website
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